POWER SEMICONDUCTOR DEVICE HAVING TRENCH GATE TYPE IGBT AND DIODE REGIONS

Abstract

Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region. Trenches formed in the first surface include a gate trench and a boundary trench disposed between the gate trench and the diode region. A fourth layer of the semiconductor substrate is provided on the first surface and has a portion included in the diode region. The fourth layer includes a trench-covering well region that covers the deepest part of the boundary trench, a plurality of isolated well regions, and a diffusion region that connects the trench-covering well region and the isolated well regions. The diffusion region has a lower impurity concentration than that of the isolated well regions. A first electrode is in contact with the isolated well regions and away from the diffusion region.

Claims

1. A power semiconductor device having a trench gate type IGBT region and a diode region for reverse conduction of said IGBT region, the power semiconductor device comprising: a semiconductor substrate having a first surface and a second surface opposite said first surface, said first surface having a portion included in said IGBT region and a portion included in said diode region, said semiconductor substrate including, a first layer of a first conductivity type that is provided on said first surface and away from said second surface in said IGBT region, a second layer of a second conductivity type that is provided on said first surface and away from said second surface in said IGBT region, said second conductivity type being different from said first conductivity type, a third layer of said second conductivity type that is provided away from said first surface and said second surface in said IGBT region and in contact with said first layer and said second layer, a fourth layer of said second conductivity type that has a portion included in said diode region and is provided on said first surface and away from said second surface, a fifth layer of said first conductivity type that is in contact with said third layer in said IGBT region and is in contact with said fourth layer in said diode region, a sixth layer of said second conductivity type that is provided on said second surface, is at least partially included in said IGBT region, and is in contact with said fifth layer, and a seventh layer of said first conductivity type that is provided on said second surface, is at least partially included in said diode region, and is in contact with said fifth layer, said first surface of said semiconductor substrate being provided with a plurality of trenches each having a side wall, said plurality of trenches including a gate trench and a boundary trench, said gate trench having a gate side wall that has a surface formed of said first layer, said third layer, and said fifth layer as said side wall, and said boundary trench being disposed between said gate trench and said diode region and having a boundary side wall that faces said diode region; a gate insulating film that covers said side walls of said trenches; a trench electrode provided in said trenches via said gate insulating film; an interlayer insulating film provided on said first surface of said semiconductor substrate and having an IGBT opening and a diode opening, said IGBT opening exposing said first layer and said second layer, and said diode opening exposing part of said fourth layer; a first electrode that is provided on said interlayer insulating film, is in contact with said first layer and said second layer through said IGBT opening, and is in contact with said fourth layer through said diode opening; and a second electrode that is provided on said second surface of said semiconductor substrate and is in contact with said sixth layer and said seventh layer, wherein said fourth layer includes a trench-covering well region that covers a deepest part of said boundary side wall, a plurality of isolated well regions that are disposed separately from said trench-covering well region, a diffusion region that connects said trench-covering well region and said plurality of isolated well regions, and a high-concentration region, said diffusion region having a lower impurity concentration than impurity concentrations of said trench-covering well region and said isolated well regions and said high-concentration region having a higher impurity concentration than impurity concentrations of said trench-covering well region and said isolated well regions when impurity concentrations in a direction parallel to said first surface of said semiconductor substrate are compared, and wherein said first electrode is in contact with only said high-concentration region of said fourth layer.

2. The power semiconductor device according to claim 1, wherein said high-concentration region is disposed on said diffusion region and spaced from said trench-covering well region and said isolated well regions in said fourth layer.

3. A power semiconductor device having an IGBT region that includes a plurality of cells, and a diode region for reverse conduction of said IGBT region, the power semiconductor device comprising: a semiconductor substrate having a first surface and a second surface opposite said first surface, said first surface having a portion included in said IGBT region and a portion included in said diode region, said semiconductor substrate including, a first layer of a first conductivity type that is provided on said second surface and is at least partially included in said diode region, a second layer of said first conductivity type that is in contact with said first layer in said diode region, and a third layer of a second conductivity type that is provided on said first surface and away from said second surface, is at least partially included in said diode region, and is in contact with said second layer, said second conductivity type being different from said first conductivity type; an interlayer insulating film that is provided on said first surface of said semiconductor substrate and has a diode opening that exposes part of said third layer; a first electrode that is provided on said interlayer insulating film and is in contact with said third layer through said diode opening; and a second electrode that is provided on said second surface of said semiconductor substrate and is in contact with said first layer, wherein said third layer includes a first region and a plurality of second regions, said first region being provided on the whole of said first surface in said diode region, said plurality of second regions being spaced from each other on said first region, and said second region having a higher impurity concentration than an impurity concentration of said first region when impurity concentrations in a direction parallel to said first surface of said semiconductor substrate are compared, and wherein said first electrode is in contact with only said second region of said third layer.

4. A power semiconductor device having an IGBT region and a diode region for reverse conduction of said IGBT region, the power semiconductor device comprising: a semiconductor substrate having a first surface and a second surface opposite said first surface, said first surface having a portion included in said IGBT region and a portion included in said diode region, said semiconductor substrate including, a first layer of a first conductivity type that is provided on said second surface and is at least partially included in said diode region, a second layer of said first conductivity type that is in contact with said first layer in said diode region, and a third layer of a second conductivity type that is provided on said first surface and away from said second surface, is at least partially included in said diode region, and is in contact with said second layer, said second conductivity type being different from said first conductivity type; an interlayer insulating film that is provided on said first surface of said semiconductor substrate and has a diode opening that exposes part of said third layer; a first electrode that is provided on said interlayer insulating film and is in contact with said third layer through said diode opening; and a second electrode that is provided on said second surface of said semiconductor substrate and is in contact with said first layer, wherein said third layer includes a first region, a second region that is disposed away from said first region, and a diffusion region that connects said first region and said second region, said second region having a higher impurity concentration than an impurity concentration of said first region and said diffusion region having a lower impurity concentration than impurity concentrations of said first region and said second region when impurities in a direction parallel to said first surface of said semiconductor substrate are compared, and wherein said first electrode is in contact with only said second region of said third layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG. 1 is a plan view schematically illustrating a configuration of a power semiconductor device according to a first preferred embodiment of the present invention; FIG. 2 is a partial plan view schematically illustrating a broken-line portion II in FIG. 1;

[0037] FIG. 3 is a schematic partial cross-sectional view taken along line in FIG. 2;

[0038] FIG. 4 is a schematic partial cross-sectional view taken along line IV-IV in FIG. 2;

[0039] FIG. 5 is a partial plan view schematically illustrating a configuration of a power semiconductor device according to a second preferred embodiment of the present invention;

[0040] FIG. 6 is a schematic partial cross-sectional view taken along line VI-VI in FIG. 5;

[0041] FIG. 7 is a schematic partial cross-sectional view taken along line VII-VII in FIG. 5;

[0042] FIG. 8 is a partial plan view schematically illustrating a configuration of a power semiconductor device according to a third preferred embodiment of the present invention;

[0043] FIG. 9 is a schematic partial cross-sectional view taken along line IX-IX in FIG. 8;

[0044] FIG. 10 is a schematic partial cross-sectional view taken along line X-X in FIG. 8;

[0045] FIG. 11 is a partial plan view schematically illustrating a configuration of a power semiconductor device according to a fourth preferred embodiment of the present invention;

[0046] FIG. 12 is a partial plan view schematically illustrating a configuration of a power semiconductor device according to a fifth preferred embodiment of the present invention;

[0047] FIG. 13 is a schematic partial cross-sectional view taken along line XIII-XIII in FIG. 12;

[0048] FIG. 14 is a schematic partial cross-sectional view taken along line XIV-XIV in FIG. 12;

[0049] FIG. 15 is a partial plan view schematically illustrating a configuration of a power semiconductor device according to a sixth preferred embodiment of the present invention;

[0050] FIG. 16 is a schematic partial cross-sectional view taken along line XVI-XVI in FIG. 15;

[0051] FIG. 17 is a schematic partial cross-sectional view taken along line XVII-XVII in FIG. 15;

[0052] FIG. 18 is a partial plan view schematically illustrating a configuration of a power semiconductor device according to a seventh preferred embodiment of the present invention;

[0053] FIG. 19 is a schematic partial cross-sectional view taken along line XIX-XIX in FIG. 18; and

[0054] FIG. 20 is a schematic partial cross-sectional view taken along line XX-XX in FIG. 18.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0055] Preferred embodiments of the present invention will be described hereinafter with reference to the drawings. Note that constituent elements that are identical to or correspond to one another are denoted by the same reference numerals, and redundant descriptions thereof will be omitted.

First Preferred Embodiment

[0056] Referring to FIG. 1, an RC-IGBT (power semiconductor device) 91 according to the present preferred embodiment includes an IGBT region 81, an FWD region 82 (diode region), and an outer peripheral region 83 in a plan layout. The IGBT region 81 is of a trench gate type. The FWD region 82 is a region for reverse conduction of the IGBT region 81. Note that an interconnection structure including, for example, a metal gate interconnection region or a gate pad is not illustrated in FIG. 1.

[0057] FIG. 2 is a schematic partial plan view illustrating a structure of a broken-line portion II of the RC-IGBT 91 in FIG. 1. FIGS. 3 and 4 are schematic partial cross-sectional views taken respectively along lines and IV-IV in FIG. 2. To facilitate viewing, part of the structure that is located in the upper part in FIGS. 3 and 4 is not illustrated in FIG. 2. Referring to FIGS. 2 to 4, the RC-IGBT 91 includes a semiconductor substrate 71, a gate oxide film 8 (gate insulating film), a trench electrode 9, an interlayer insulating film 10, an emitter electrode 11 (first electrode), and a collector electrode 12 (second electrode).

[0058] The semiconductor substrate 71 has a top surface S1 (first surface) and a back surface S2 (second surface opposite the first surface). The top surface S1 and the back surface S2 each have a portion included in the IGBT region 81 and a portion included in the FWD region 82. The semiconductor substrate 71 includes an n.sup.+ emitter layer 4 (first layer) of an n type (first conductivity type), a p.sup.+ contact layer 5 (second layer) of a p type (second conductivity type different from the first conductivity type), a p base layer 2 (third layer) of the p type, a p layer 41 (fourth layer) of the p type, an n layer 50 (fifth layer) of the n type, a p.sup.+ collector layer 6 (sixth layer) of the p type, and an n.sup.+ cathode layer 7 (seventh layer) of the n type.

[0059] The n.sup.+ emitter layer 4 is provided on the top surface S1 and away from the back surface S2 in the IGBT region 81. The p.sup.+ contact layer 5 is provided on the back surface S2 and away from the top surface S1 in the IGBT region 81. The p base layer 2 is provided away from the top surface S1 and the back surface S2 in the IGBT region 81. The p base layer 2 is in contact with the n.sup.+ emitter layer 4 and the p.sup.+ contact layer 5. The p layer 41 has a portion included in the FWD region 82 and is provided on the top surface S1 and away from the back surface S2. The n layer 50 is in contact with the p base layer 2 in the IGBT region 81 and in contact with the p layer 41 in the FWD region 82. The p.sup.+ collector layer 6 and the n.sup.+ cathode layer 7 are provided on the back surface S2 and are in contact with the n layer 50. The p.sup.+ collector layer 6 is at least partially included in the IGBT region 81, and the n.sup.+ cathode layer 7 is at least partially included in the FWD region 82.

[0060] The n layer 50 includes an n.sup. drift layer 1. A portion of the n layer 50 that is in contact with the p base layer 2 is preferably a carrier storing layer 3 that has a higher impurity concentration than that of the n.sup. drift layer 1. A portion of the n layer 50 that is in contact with the p.sup.+ collector layer 6 or the n.sup.+ cathode layer 7 is preferably a buffer layer 13 that has a higher impurity concentration than that of the n.sup. drift layer 1.

[0061] The top surface S1 of the semiconductor substrate 71 is provided with a plurality of trenches TR each having a side wall. The trenches TR include gate trenches and a boundary trench (the right-most trench among the trenches TR in FIG. 3 or 4) disposed between the gate trenches and the FWD region 82. The gate trenches each have a gate side wall having a channel surface formed of the n.sup.+ emitter layer 4, the p base layer 2, and the n layer 50, as a side wall. The boundary trench has a boundary side wall (the right-side wall in FIG. 3 or 4) that faces the FWD region 82 as a side wall.

[0062] The gate oxide film 8 covers the side walls of the trenches TR. The trench electrode 9 is provided in the trenches TR via the gate oxide film 8. The trench electrode 9 is made of, for example, polysilicon.

[0063] The interlayer insulating film 10 is provided on the top surface S1 of the semiconductor substrate 71. The interlayer insulating film 10 has IGBT contact holes CI (IGBT openings) that expose the n.sup.+ emitter layer 4 and the p.sup.+ contact layer 5, and diode contact holes CF and CB (diode openings) that expose part of the p layer 41.

[0064] The emitter electrode 11 is provided on the interlayer insulating film 10. The emitter electrode 11 is in contact with the n.sup.+ emitter layer 4 and the p.sup.+ contact layer 5 through the IGBT contact holes CI and is in contact with the p layer 41 through the diode contact holes CF and CB.

[0065] The collector electrode 12 is provided on the back surface S2 of the semiconductor substrate 71. The collector electrode 12 is in contact with the p.sup.+ collector layer 6 and the n.sup.+ cathode layer 7.

[0066] The p layer 41 includes a trench-covering well region 16B, a plurality of isolated well regions 16F, and a diffusion region 17. The trench-covering well region 16B covers the deepest part of the boundary side wall (the side wall of the right-most trench TR in FIG. 3 or 4) of the aforementioned boundary trench. In other words, the trench-covering well region 16B covers a corner portion of the boundary trench on the FWD region side. The isolated well regions 16F are each disposed separately from the trench-covering well region 16B. The isolated well regions 16F are also spaced from one another. The width (lateral dimension in FIG. 3 or 4) of each isolated well region 16F is smaller than that of the trench-covering well region 16B. The diffusion region 17 connects the trench-covering well region 16B and the isolated well regions 16F. The p layer 41 is preferably formed on the entire top surface S1 in the FWD region 82.

[0067] When impurity concentrations in a direction parallel to the top surface S1 of the semiconductor substrate 71 are compared, the diffusion region 17 has a lower impurity concentration than those of the trench-covering well region 16B and the isolated well regions 16F. Thus, the impurity concentration of the p layer 41 at the top surface S1 varies.

[0068] The diode contact holes CF and CB of the interlayer insulating film 10 respectively expose the isolated well regions 16F and the trench-covering well region 16B. With this structure, the emitter electrode 11 is in contact with only the isolated well regions 16F and the trench-covering well region 16B of the p layer 41 and is away from the diffusion region 17.

[0069] Next, a method of manufacturing the RC-IGBT 91, and in particular, the process of forming the p layer 41 will be described below.

[0070] First, ion-implanted regions IJ are formed by selectively implanting impurity ions into the top surface S1 of the semiconductor substrate 71. The positions of the ion-implanted regions IJ on the top surface S1 correspond to the positions of the trench-covering well region 16B and the isolated well regions 16F. The depth of the ion-implanted region IJ that corresponds to the trench-covering well region 16B and the depth of the ion-implanted regions IJ that correspond to the isolated well regions 16F are approximately the same at the time immediately after the ion implantation.

[0071] The above-described formation of the ion-implanted regions IJ can be performed collectively by using an implantation mask that is formed using common lithographic technology. The ions implanted are boron, for example.

[0072] Next, the implanted impurities are diffused by heat treatment. This diffusion occurs in the direction parallel to the top surface S1 (lateral direction in FIGS. 3 and 4) and in the depth direction perpendicular to the former direction. This results in the formation of the trench-covering well region 16B and the isolated well regions 16F that are shallower than the trench-covering well region 16B. The diffusion occurring in the direction parallel to the top surface S1 also results in the formation of the diffusion region 17 having a relatively low impurity concentration between the ion-implanted regions IJ, and reduces the impurity concentration of the isolated well regions 16F. Here, the width (lateral dimension in FIGS. 3 and 4) of the trench-covering well region 16B is sufficiently greater than the width of each isolated well region 16F. This suppresses a reduction in the impurity concentration of the trench-covering well region 16B due to the diffusion.

[0073] As described above, the trench-covering well region 16B located at the boundary between the IGBT region 81 and the FWD region 82, and the isolated well regions 16F and the diffusion region 17 that are located adjacent to the trench-covering well region 16B in the FWD region 82 and have lower impurity concentrations than that of the trench-covering well region 16B are collectively formed on the top surface S1 of the semiconductor substrate 71. Note that the diffusion region 17 is a region in which impurities are introduced by the diffusion rather than the ion implantation. Thus, when compared in the top surface S1, the impurity concentration of the diffusion region 17 is lower than those of the trench-covering well region 16B and the isolated well regions 16F.

[0074] The average impurity concentration of the isolated well regions 16F and the diffusion region 17 can be adjusted depending on the pattern of the ion-implanted regions IJ on the top surface S1, and in particular, can be adjusted depending on the dimension of the width of the pattern and the intervals in the pattern. The pattern adjustment allows the entire top surface S1 in the diode region 82 to be of the p type after the diffusion process. For example, when the average surface impurity concentration of the isolated well regions 16F and the diffusion region 17 is set to be 510.sup.16/cm.sup.3 on condition that the surface impurity concentration of the trench-covering well region 16B is 110.sup.18/cm.sup.3, the ratio of the isolated well regions 16F occupying the top surface S1 in the FWD region 82 can be set to 1/20. For example, when the isolated well regions 16F are disposed in the form of a square on the top surface S1, 1.0-m-squre isolated well regions 16F can be formed within a square with edges of 20.sup.1/2 m4.5 m. The average impurity concentration of the isolated well regions 16F and the diffusion region 17 is preferably set to be greater than or equal to 110.sup.16/cm.sup.3 and less than or equal to 110.sup.18/cm.sup.3. In this case, it is possible to avoid problems such as a reduction in withstand voltage and to keep an appropriate balance between maintaining good recovery characteristics and suppressing a forward voltage drop.

[0075] According to the present preferred embodiment, the diffusion region 17 having a lower impurity concentration than those of the trench-covering well region 16B and the isolated well regions 16F is formed in the p layer 41. Consequently, the average impurity concentration of the p layer 41 is reduced as compared to the case where the p layer 41 as a whole is formed with only the impurity concentrations of the trench-covering well region 16B and the isolated well regions 16F. This suppresses the recovery current in the FWD region 82.

[0076] On the other hand, the emitter electrode 11 is disposed away from the diffusion region 17 having a lower impurity concentration, and is in contact with only the isolated well regions 16F and the trench-covering well region 16B that have higher impurity concentrations. This ensures good ohmic contact and prevents the forward voltage in the FWD region 82 from increasing due to a voltage drop in a portion of contact between the emitter electrode 11 and a portion of the p layer 41 that has a low impurity concentration (specifically, the diffusion region 17).

[0077] From the above, the FWD region 82 can combine both a low forward voltage and a low recovery current. Using this FWD region 82 as a free-wheeling diode of the IGBT region 81 can reduce the switching loss of the RC-IGBT 91.

[0078] Note that the effect of the trench-covering well region 16B preventing dielectric breakdown in the corner portion of the boundary trench (the lower-right corner portion of the right-most trench TR in FIG. 3 or 4) will be reduced if the impurity concentration of the trench-covering well region 16B is too low. In addition, if the trenches TR are covered with such a trench-covering well region 16B that has a low impurity concentration, the time of heat treatment for diffusing impurities will increase and manufacturing efficiency will considerably decrease. In contrast, the present preferred embodiment can maintain a high impurity concentration of the trench-covering well region 16B.

[0079] Moreover, the emitter electrode 11 is disposed away from the diffusion region 17 having a relatively low impurity concentration as described above. This eliminates places where the contact resistance is high, thus reducing the possibility of local heat generation due to the presence of such places. It is thus possible to prevent the occurrence of operational problems due to heat generation and to improve the reliability of the RC-IGBT 91.

[0080] The p.sup.+ collector layer 6 (FIGS. 3 and 4) preferably has a portion that extends from the IGBT region 81 into the FWD region 82. More specifically, the p.sup.+ collector layer 6 preferably has a portion that faces the diffusion region 17 in the depth direction of the semiconductor substrate 71, and may further have a portion that faces the isolated well regions 16F. This reduces the possibility that the trench-covering well region 16B may function as a parasitic diode. It is thus possible to improve the recovery characteristics of the FWD region 82.

[0081] With the method of manufacturing the RC-IGBT 91 according to the present preferred embodiment, the trench-covering well region 16B, the isolated well regions 16F, and the diffusion region 17 are collectively formed by selective ion implantation and diffusion performed on the top surface S 1. Thus, the structure can be formed at a low cost.

Second Preferred Embodiment

[0082] Referring to FIGS. 5 to 7, in an RC-IGBT 92 according to the present preferred embodiment, the emitter electrode 11 is in contact with only the isolated well regions 16F of the p layer 41. In other words, the interlayer insulating film 10 has no diode contact hole CB (FIGS. 3 and 4) that exposes the trench-covering well region 16B. The other constituent elements are substantially the same as those of the above-described first preferred embodiment. Thus, constituent elements that are the same as or correspond to those of the first preferred embodiment are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0083] The present preferred embodiment can achieve substantially the same effect as that of the first preferred embodiment. In addition, unlike the first preferred embodiment, the second preferred embodiment can further reduce the recovery current because the emitter electrode 11 is not in contact with the trench-covering well region 16B, which has a higher impurity concentration than that of the isolated well regions 16F. It is thus possible to further reduce the switching loss due to the recovery current in the FWD region 82.

Third Preferred Embodiment

[0084] Referring to FIGS. 8 to 10, in a semiconductor substrate 73 of an RC-IGBT 93 according to the present preferred embodiment, a p layer 43 includes a p.sup.+ region 15 (high-impurity region) in addition to a trench-covering well region 16B, a plurality of isolated well regions 16F, and a diffusion region 17. When impurity concentrations in the direction parallel to the top surface S1 of the semiconductor substrate 73 are compared, the p.sup.+ region 15 has a higher impurity concentration than those of the trench-covering well region 16B and the isolated well regions 16F. The emitter electrode 11 is in contact with only the p.sup.+ region 15 of the p layer 43.

[0085] The p layer 43 is obtained by separately performing an ion implantation process for forming the p.sup.+ region 15 in addition to the ion implantation process for forming the p layer 41 according to the first preferred embodiment. An ion-implanted region for forming the p.sup.+ region 15 is disposed so as to not overlap with the ion-implanted regions for forming the trench-covering well region 16B and the isolated well regions 16F. Thus, the p.sup.+ region 15 is disposed on the diffusion region 17 and away from the trench-covering well region 16B and the isolated well regions 16F in the p layer 43.

[0086] Note that constituent elements other than those described above are substantially the same as those of the above-described first and second embodiments. Thus, constituent elements that are the same as or correspond to those of the first and second preferred embodiments are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0087] According to the present preferred embodiment, the diffusion region 17 having a lower impurity concentration than those of the trench-covering well region 16B and the isolated well regions 16F are formed in the p layer 43. Consequently, the average impurity concentration of the p layer 43 is reduced as compared to the case where the p layer 43 as a whole is formed with the impurity concentrations of only the trench-covering well region 16B or the isolated well regions 16F. This suppresses the recovery current in the FWD region 82. On the other hand, the emitter electrode 11 is in contact with only the p.sup.+ region 15 of the p layer 43. This prevents the forward voltage in the FWD region 82 from increasing due to a voltage drop at a contact between the emitter electrode 11 and a portion of the p layer 43 that has a low impurity concentration.

[0088] From the above, the FWD region 82 can combine both a low forward voltage and a low recovery current. Using this FWD region 82 as a free-wheeling diode of the IGBT region 81 can reduce the switching loss of the RC-IGBT 93.

[0089] Moreover, according to the present preferred embodiment, the trench-covering well region 16B or the isolated well regions 16F do not overlap with the p.sup.+ region 15.

[0090] This prevents the formation of a portion where the impurity concentration locally exceeds the impurity concentration of the p.sup.+ region 15. It is thus possible to improve the recovery characteristics.

Fourth Preferred Embodiment

[0091] Referring to FIG. 11, in an RC-IGBT 94 according to the present preferred embodiment, the p.sup.+ region 15 includes portions that are in contact with the trench-covering well region 16B and the isolated well regions 16F. In other words, the ion-implanted region for forming the p.sup.+ region 15 has portions that overlap with the ion-implanted regions for forming the trench-covering well region 16B and the isolated well regions 16F during manufacture of the RC-IGBT 94.

[0092] Note that constituent elements other than those described above are substantially the same as those of the above-described third preferred embodiment. Thus, constituent elements that are the same as or correspond to those of the third preferred embodiment are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0093] Like the third preferred embodiment, the present preferred embodiment can also reduce the switching loss. In addition, unlike the third preferred embodiment, the fourth preferred embodiment has no limitations such as the need to dispose the p.sup.+ region 15 and the trench-covering well region 16B or the isolated well regions 16F on the top surface S1 without overlapping. This increases the degree of flexibility in the layout of each region. In FIG. 11, for example, the arrangement pattern of the p.sup.+ region 15 on the top surface S1 corresponds to the vertices of rectangles, and there is found no specific relationship with the arrangement pattern of the isolated well regions 16F.

[0094] Note that the interval of the isolated well regions 16F in FIG. 11 is made smaller than that in FIG. 8. Moreover, the isolated well regions 16F are arranged in a hexagonal closest packed configuration on the top surface S1 of the semiconductor substrate 73. This reduces the cycle of change in impurity concentration on the top surface of the semiconductor substrate in the FWD region 82, thus increasing the uniformity of the distribution of impurity concentrations in the top surface S1. It is thus possible to improve the recovery characteristics.

Fifth Preferred Embodiment

[0095] Referring to FIGS. 12 to 14, a semiconductor substrate 75 of an RC-IGBT 95 according to the present preferred embodiment includes an n.sup.+ cathode layer 7 (first layer), an n layer 50 (second layer), and a p layer 45 (third layer).

[0096] The p layer 45 is provided on the top surface S1 and away from the back surface S2. The p layer 45 is at least partially included in the FWD region 82 and is in contact with the n layer 50. The p layer 45 includes a p region 14 (first region) and a plurality of p.sup.+ regions 15 (second regions). The p region 14 is provided on the entire top surface S1 in the FWD region 82. The p region 14 may be collectively formed together with the p base layer 2. The p.sup.+ regions 15 are spaced from one another on the p region 14. When impurity concentrations in the direction parallel to the top surface S1 of the semiconductor substrate 75 are compared, the p.sup.+ regions 15 have a higher impurity concentration than that of the p region 14.

[0097] The interlayer insulating film 10 is provided on the top surface S1 of the semiconductor substrate 75 and has diode contact holes CF that expose part of the p layer 45. The emitter electrode 11 is provided on the interlayer insulating film 10 and is in contact with the p layer 45 through the diode contact holes CF. The emitter electrode 11 is in contact with only the p.sup.+ regions 15 of the p layer 45.

[0098] The average impurity concentration of the p layer 45 is desirably reduced to a value close to the impurity concentration of the p region 14. To achieve this, the ratio of the p.sup.+ regions 15 occupying the p region 14 may be sufficiently reduced. The p.sup.+ regions 15 are desirably arranged with small variations in distribution on the top surface S1, and for example, arranged in a hexagonal closest packed configuration as illustrated in FIG. 12.

[0099] Note that constituent elements other than those described above are substantially the same as those of the above-described first preferred embodiment. Thus, constituent elements that are the same as or correspond to those of the first preferred embodiment are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0100] According to the present preferred embodiment, the p region 14 having a lower impurity concentration than that of the p.sup.+ regions 15 is formed on the entire top surface S1 in the p layer 45 of the FWD region 82. Consequently, the p layer 45 can be formed with a low impurity concentration and high uniformity in the FWD region 82. This suppresses the recovery current in the FWD region 82.

[0101] On the other hand, the emitter electrode 11 is in contact with only the p.sup.+ regions 15 of the p layer 45. This prevents the forward voltage in the FWD region 82 from increasing due to a voltage drop at a contact between the emitter electrode 11 and a portion of the p layer 45 that has a low impurity concentration.

[0102] From the above, the FWD region 82 can combine both a low forward voltage and a low recovery current. Using this FWD region 82 as a free-wheeling diode of the IGBT region 81 can reduce the switching loss of the RC-IGBT 95.

[0103] In addition, when the IGBT region 81 includes a plurality of cells, it is possible for cells that have other cells adjacent thereto to avoid a situation where they are adjacent to the n.sup.+ cathode layer 7 on the back surface S2. In other words, no anode-short structures are formed. Thus, snapback does not occur during forward bias operation in the FWD region 82. It is thus possible to suppress an increase in steady-state loss due to snapback.

Sixth Preferred Embodiment

[0104] Referring to FIGS. 15 to 17, a semiconductor substrate 76 of an RC-IGBT 96 according to the present preferred embodiment has trenches TR and a carrier storing layer 3 in not only the IGBT region 81 but also the FWD region 82. The p layer 45 is disposed on the carrier storing layer 3, and the trenches TR pass through both of these layers.

[0105] Note that constituent elements other than those described above are substantially the same as those of the above-described fifth preferred embodiment. Thus, constituent elements that are the same as or correspond to those of the fifth preferred embodiment are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0106] According to the present preferred embodiment, the carrier storing layer 3 disposed under the p layer 45 can suppress the implantation of carriers from the p layer 45. This further suppresses the recovery current. In addition, the trenches TR formed in the FWD region 82 allows a high withstand voltage to be kept in a state in which the carrier storing layer 3 is disposed in the FWD region 82.

Seventh Preferred Embodiment

[0107] Referring to FIGS. 18 to 20, in a semiconductor substrate 77 of an RC-IGBT 97 according to the present preferred embodiment, a p layer 47 includes a p region 14 (first region), a p.sup.+ region 15 (second region) that is disposed away from the p region 14, and a diffusion region 18 that connects the p region 14 and the p.sup.+ region 15. When impurity concentrations in the direction parallel to the top surface S1 of the semiconductor substrate 77 are compared, the diffusion region 18 has a lower impurity concentration than those of the p region 14 and the p.sup.+ region 15. The emitter electrode 11 is in contact with only the p.sup.+ region 15 of the p layer 47.

[0108] Note that constituent elements other than those described above are substantially the same as those of the above-described fifth preferred embodiment. Thus, constituent elements that are the same as or correspond to those of the fifth preferred embodiment are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0109] According to the present preferred embodiment, the diffusion region 18 having a lower impurity concentration than those of the p region 14 and the p.sup.+ region 15 is formed in the p layer 47. Consequently, the average impurity concentration of the p layer 47 is reduced as compared to the case where the p layer 47 as a whole is formed with only the impurity concentrations of the p region 14 or the p.sup.+ region 15. This suppresses the recovery current in the FWD region 82. On the other hand, the emitter electrode 11 is in contact with only the second impurity region of the p layer 47. This prevents the forward voltage in the FWD region 82 from increasing due to a voltage drop at a contact between the emitter electrode 11 and a portion of the p layer 47 that has a low impurity concentration. From the above, the FWD region 82 can combine both a low forward voltage and a low recovery current. Using this FWD region 82 as a free-wheeling diode of the IGBT region 81 can reduce the switching loss of the RC-IGBT 97.

[0110] In addition, the p region 14 and the p.sup.+ region 15 do not overlap each other. This prevents the formation of a portion where the impurity concentration locally exceeds the impurity concentration of the p.sup.+ region 15. It is thus possible to further improve the recovery characteristics.

[0111] The p layer 47 is preferably formed on the entire top surface S1 in the FWD region 82. In this case, it is possible to maintain the withstand voltage more favorably.

[0112] It should be noted that the present invention can be implemented by freely combining embodiments described above or by making modifications or omissions on those embodiments as appropriate without departing from the scope of the present invention. For example, the gate structure of the IGBT region may be of a plane type rather than of a trench type. The carrier storing layer may be omitted. While the above-described embodiments take the example of the case where the first conductivity type is regarded as the n type and the second conductivity type as the p type, these types may be substituted for each other.

[0113] While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore to be understood that numerous modifications and variations can be devised without departing from the scope of the invention.