A semiconductor device is provided, including: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region provided on the semiconductor substrate and arranged sandwiching the active portion in a top view; a peripheral well region provided on the semiconductor substrate and arranged enclosing the active portion in a top view; an intermediate well region provided on the semiconductor substrate and arranged between the first well region and the second well region in a top view; a first pad arranged above the first well region and a second pad arranged above the second well region; and a temperature sense diode arranged above the intermediate well region.

A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, wherein the silicon carbide layer comprises a doping region to be produced, forming an electrically conductive contact structure on the surface of the silicon carbide layer, the electrically conductive contact structure, producing a splitting region by pre-damaging the splitting region, wherein the splitting region is produced by laser treating the splitting region before forming the electrically conductive contact, splitting the silicon carbide layer or the initial wafer along the splitting region such that a silicon carbide substrate of the silicon carbide component to be produced is split off, wherein the silicon carbide substrate has a thickness of more than 30 m, wherein the doping region extends to a surface of the silicon carbide layer before splitting the silicon carbide layer, and wherein splitting along comprises applying a polymer film.

A semiconductor module includes: a first power semiconductor element that includes a first main current electrode; a main body that accommodates therein the first power semiconductor element; and a first main current terminal connectable to the first main current electrode. The main body includes: a top face; a side face that connects to the top face; a bottom face fixable to a cooler; and a recessed portion that is on the side face, and accommodates therein an end portion of an insulating member. The first main current terminal protrudes from the side face of the main body, and includes: a first face; and a second face on an opposite side of the first face. The second face is closer to the bottom face than the first face on the side face. The recessed portion is on the side face between the bottom face and the second face, and is at a position apart from the bottom face.

A semiconductor device comprises a switching device and a cathode pad disposed in a semiconductor die and a termination structure disposed between the switching device and the cathode pad. The switching device comprises a first conduction terminal on a top surface of the semiconductor die, and a second conduction terminal disposed on a bottom surface of the semiconductor die. A drift layer of the semiconductor die may be disposed between the first and second conduction terminals. The cathode pad is disposed on the top surface and electrically connected to the drift layer, and corresponds to a cathode terminal of a diode having the first conduction terminal as an anode terminal. The diode operates as a free-wheeling diode for the switching device when the cathode pad is electrically coupled to the second conduction terminal. Accordingly, the semiconductor device may operate as a Reverse-Conducting Insulated Gate Transistor having reduced snapback.

A semiconductor device includes a silicon carbide layer including an element region, a termination region surrounding the element region, a first semiconductor part including a first portion in the element region, and a second semiconductor part located on the first semiconductor part in a first direction, the second semiconductor part being adjacent to the first portion in a second direction; a gate electrode facing the second semiconductor part of the element region; a first insulating film located between the gate electrode and the silicon carbide layer; and a second insulating film located on the first portion of the first semiconductor part, the second insulating film being thicker than the first insulating film.

A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants that define a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.

A semiconductor device includes an element region and a termination region. The element region includes a first semiconductor region of a first conductivity type located on a first electrode and a second semiconductor region of a second conductivity type located on the first semiconductor region. The second semiconductor region is electrically connected with a second electrode. The termination region includes a third semiconductor region of the first conductivity type, a first diffusion layer of the second conductivity type located at a surface of the third semiconductor region, and a second diffusion layer of the second conductivity type. The third semiconductor region is located outward of the first semiconductor region. The first diffusion layer surrounds the element region. The second diffusion layer surrounds the element region, and is deeper than the first diffusion layer.

A semiconductor device includes a semiconductor layer of a first conductivity type having a first principal surface on one side and a second principal surface on the other side, the semiconductor layer in which a device formation region and an outer region outside the device formation region are set, a channel region of a second conductivity type formed in a surface layer portion of the first principal surface of the semiconductor layer in the device formation region, an emitter region of a first conductivity type formed in a surface layer portion of the channel region, a gate electrode formed at the first principal surface of the semiconductor layer in the device formation region, the gate electrode facing the channel region across a gate insulating film, a collector region of a second conductivity type formed in a surface layer portion of the second principal surface of the semiconductor layer in the device formation region, an inner cathode region of a first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the device formation region, and an outer cathode region of a first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the outer region.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that includes a drift region having a first conductivity type, a plurality of channel regions that each have a second conductivity type, and a plurality of JFET regions that each have the first conductivity type. Each channel region comprises a ring-shaped channel region that has a ring shape and surrounds a respective one of the JFET regions when viewed in plan view.