A semiconductor device of an embodiment includes a semiconductor substrate that includes a first principal surface and a second principal surface, the first principal surface and the second principal surface facing each other in a first direction, a drift region, a buffer region that includes a plurality of concentration peaks, a first electrode provided on the first principal surface, a second electrode provided on the second principal surface, and a transistor region, in which the plurality of concentration peaks includes a first concentration peak that is disposed closest to the second principal surface, a second concentration peak that is disposed farther from the second principal surface than the first concentration peak and has a higher impurity concentration than that of the first concentration peak, and a third concentration peak that is selectively providedbetween the first principal surface and the second concentration peak.

Two or more IGBTs (insulated gate bipolar transistors) formed in or on a 4H silicon carbide (SiC) A-plane <1120> substrate of a first type. A merge layer is formed in the SiC substrate. The merge layer comprises an epitaxial layer of the first type formed by on-axis epitaxial lateral overgrowth. At least one epitaxial layer is formed overlying a surface of the merge layer. The at least one epitaxial layer is of a second type and at least 25 microns thick. The at least one epitaxial layer is formed by vertical epitaxial overgrowth. The at least one epitaxial layer is at least 25 microns thick and is a drift layer for the two or more IGBTs. An exfoliation process is configured to separate the SiC substrate at the merge layer from the two or more IGBTs. The SiC substrate is prepared and reused to form other semiconductor devices.

A semiconductor device of embodiments includes: a transistor region including a semiconductor layer having a first face and a second face opposite to the first face, a first transistor having a first gate electrode provided on a first face side of the semiconductor layer, and a second transistor having a second gate electrode provided on a second face side of the semiconductor layer; and an adjacent region adjacent to the transistor region and including the semiconductor layer and a third transistor having a third gate electrode electrically connected to the second gate electrode and provided on the second face side of the semiconductor layer and the third transistor having an absolute value of a threshold voltage smaller than an absolute value of a threshold voltage of the second transistor.

A method for reducing parasitic junction field effect transistor resistance, applicable to a high power device having a semiconductor substrate layer, is provided, including providing a plurality of hard masks on a top surface of the semiconductor substrate layer. Each hard mask has a bottom plane and a tilt sidewall such that an acute angle is formed there in between. A body ion implantation process is subsequently performed, so a body region is formed between two adjacent hard masks. The body region has an upper and a lower surface. A width of the upper surface is greater than that of the lower surface. Therefore, the present invention achieves to control a parasitic JFET region characterized by having a wider bottom and a narrower top, thereby reducing its resistance thereof. Meanwhile, since a bottom angle of the body region is increased, breakdown voltage of the device is increased as well.

The disclosure provides a power semiconductor device and manufacturing method thereof. A plurality of second resistive field plate structures extending through an epitaxial layer in a first direction into a substrate are arranged in a termination region of the epitaxial layer and the plurality of second resistive field plate structures are arranged radially in a first plane. A plurality of tightly coupled second resistive field plates extending from a side close to a cell region to a side far away from the cell region form a more uniform three-dimensional electric field distribution diverging around the cell region, which optimizes a guiding and binding effect on a charge in a space depletion region of the cell region and improves a withstand voltage performance of the whole power semiconductor device.

A semiconductor device includes an insulating layer, a semiconductor layer on the insulating layer, and a control electrode on the semiconductor layer. The semiconductor layer includes first and second semiconductor parts and a separation trench between the first and second semiconductor parts. The first and second semiconductor parts extending along the insulating film. The first semiconductor part includes first and second regions of a first conductivity type, and a fifth region of a second conductivity type between the first and second regions. The second semiconductor part includes third and fourth regions of the second conductivity type, and a sixth region of the second conductivity type between the third and fourth regions. The control electrode extends over the fifth and sixth regions. The semiconductor layer further including a seventh region of the second conductivity type at a bottom of the separation trench and electrically connecting the fifth and sixth regions.

Provided is a method for manufacturing a semiconductor device, the method including: performing first ion implantation ion-implanting a p-type impurity into a silicon carbide layer; performing second ion implantation ion-implanting carbon (C) into the silicon carbide layer; performing a first heat treatment activating the p-type impurity; performing a first oxidation treatment oxidizing the silicon carbide layer; performing an etching treatment etching the silicon carbide layer in an atmosphere containing hydrogen gas; forming a first metal film containing at least one metal element selected from the group consisting of nickel, palladium, platinum, and chromium; performing a second heat treatment causing the silicon carbide layer to react with the first metal film to form a metal silicide layer containing the at least one metal element; and forming a second metal film having a chemical composition different from a chemical composition of the first metal film.

A semiconductor device includes a substrate, drift, source, gate and base regions, and a drain portion. The substrate is doped with a first dopant type. The drift region is disposed above the semiconductor substrate, and is doped with the first dopant type at a lower concentration. The source region is doped with the first dopant type. The gate region is disposed above the drift region and part of the source region. The base region is disposed between the source and drift regions. The base region includes a first trench extending in a first direction, and a second trench extending in a second direction and intersecting the first trench. The trenches extend into a top surface of the base region. Each trench has at least a vertical wall and at least a horizontal wall. The base region conduct current on the vertical and horizontal walls of the trenches.

To realize a highly reliable IGBT that suppresses the bipolar degradation by preventing the occurrence of a defect on a boundary between a contact region and a silicide layer. As a means to realize the above, a semiconductor device includes: a collector region that is formed on a lower surface of a semiconductor substrate and forms an IGBT; and a collector electrode that is formed on a lower surface of the collector region via a silicide layer. The collector region and the silicide layer contains aluminum, first metal being more easily bondable to silicon than aluminum, and second metal being more easily bondable to carbon than aluminum.

A power semiconductor device comprises a semiconductor body with a top side, and a main electrode and an adjacent gate electrode thereon. The semiconductor body comprises a drift layer of a first conductivity type, a base region of a second conductivity type between the drift layer and the top side, a contact region of the first conductivity type between the drift layer and the top side. The contact region adjoins the base region and the top side. The semiconductor body comprises a drift region of the first conductivity type arranged next to and adjoining the base region. The main electrode is in electrical contact with the contact region. The gate electrode at least partially covers a channel portion of the base region, which lies between the contact region and the drift region. At least one of the contact region and the drift region projects beyond the base region.