According to one embodiment, wafer includes a substrate including silicon carbide. The substrate includes a first face and a second face. The substrate includes a first region between the second face and the first face in a first direction from the second face to the first face, a second region between the second face and the first region in the first direction, and a third region between the first region and the first face in the first direction. The substrate includes nitrogen. The first region includes a first element including at least one selected from the group consisting of phosphorus and arsenic. A first concentration of the first element in the first region is higher than a second concentration of the first element in the second region, and higher than a third concentration of the first element in the third region.

According to one embodiment, wafer includes a substrate including silicon carbide. The substrate includes a first face and a second face. The substrate includes a first region between the second face and the first face in a first direction from the second face to the first face, a second region between the second face and the first region in the first direction, and a third region between the first region and the first face in the first direction. The first region includes a first element including at least one selected from the group consisting of fluorine and oxygen. A first concentration of the first element in the first region is higher than a second concentration of the first element in the second region, and higher than a third concentration of the first element in the third region.

A semiconductor device including a semiconductor layer, a trench gate structure and a buffer layer is provided. The semiconductor layer has a first surface and a second surface. The trench gate structure is at least partially located in a trench on the first surface of the semiconductor layer. The semiconductor layer includes a source region, a drift region and a body region. The buffer layer is a heterogeneous epitaxial layer of the semiconductor layer and covers an inner surface of the trench and the first surface of the semiconductor layer. The buffer layer is located between a gate dielectric layer of the trench gate structure and the semiconductor layer. By serving a heterogeneous epitaxial layer of the semiconductor layer as the buffer layer to form a reliable gate dielectric layer, the formation of carbon cluster in the gate dielectric layer is suppressed, and the reliability of the device is enhanced.

The semiconductor device according to the present disclosure has features (1) to (3) below. The feature (1) is that a lower surface of an on-chip bonding material has a shape matching a surface shape of a main current wiring connection region in plan view. The feature (2) is that an emitter sense wiring is directly connected to a side surface of the main current wiring connection region. The feature (3) is that an IGBT chip has an ineffective region in which the IGBT does not function in a region below an emitter sense pad and the emitter sense wiring.

A method for producing a power semiconductor component includes: providing a power semiconductor partial structure having an insulating layer arranged on an upper side of a semiconductor body and a contact hole proceeding from an upper side of the insulating layer, extending at least partly within the insulating layer and configured for electrical contacting of a contact region below the upper side; at least partly covering the upper side and a surface of the contact hole with an adhesion promoter layer; at least partly covering the adhesion promoter layer with a tungsten-comprising layer having a first thickness dimensioned such that the tungsten-comprising layer fills the contact hole; removing part of the tungsten-comprising layer in a region of the upper side such that the tungsten-comprising layer has a second thickness in the upper side region that is less than the first thickness; and applying a connection layer to the tungsten-comprising layer.

A semiconductor device includes a substrate comprising a first surface and a second surface positioned on an opposite side of the substrate. A first gate structure is located above the first surface of the substrate and a second gate structure is located above the first surface of the substrate, adjacent to the first gate structure. A first dielectric layer covers the first gate structure, the second gate structure, and the first surface of the substrate. The first dielectric layer has a first opening between the first gate structure and the second gate structure. A current spreading layer is located at a bottom of the first opening. The current spreading layer has a first width approximately equal to a width of the bottom of the first opening. A conductive plug is located between the first gate structure and the second gate structure and in contact with the current spreading layer.

A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer (12) is formed on the surface of the drift layer of the first layer by means of CVD growth, the drift layer of the first layer is formed by means of epitaxial growth, and accordingly, defects occurring at a junction interface of the semiconductor substrate including the single crystal SiC layer and the polycrystal SiC layer are suppressed, and manufacturing costs are also reduced.

A power semiconductor device and method for production thereof is specified involving an electrode, a base layer of a first conductivity type provided on the electrode, at least one contact layer provided on the base layer, a gate contact provided on the base layer and on the at least one contact layer, an insulation layer between the gate contact and the base layer and between the at least one contact layer and the gate contact, and at least one zone of a second conductivity type within the base layer, wherein the at least one zone is constructed and arranged to shift away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device having a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.

A fabrication method for forming a terraced gate oxide and the formed terraced gate oxide structure are provided. Sidewall barrier layers are provided in a high power device after high-temperature JFET ion implementation process. A second ion implementation process is subsequently applied under room temperatures to form an amorphous layer at the JFET top surface. After removing hard masks and sidewall barrier layers, rest processes are carried out. As for growing the gate oxide, since oxidation rate of the amorphous layer is greatly higher than that of the channel region and of the JFET region, a terraced gate oxide structure can be fabricated. Meanwhile, a bottom of the terraced gate oxide structure is underneath the device surface. The present invention is thus advantageous of reducing both the parasitic gate to drain capacitance and corner curvature of the gate electrode, thereby reduce electric field enhancement effects and avoid reliability degradation.