A power semiconductor device and a preparation method therefor. The power semiconductor device comprises: a first lateral current spreading layer (120); and a device layer (130). The device layer (130) comprises: a plurality of active doped regions (1302); and second lateral current spreading layers (1301), without overlapping projections from the second lateral current spreading layer (1301) and the device layer between adjacent active doped regions (1302) in a direction perpendicular to a surface of the semiconductor substrate layer (100), and the doping concentration of the second lateral current spreading layers (1301) is greater than the doping concentration of the drift layer (110). The power semiconductor device takes both low specific on-resistance and high reliability into consideration.

Provided is a reverse-conducting IGBT chip including a first conductive type substrate; and several first conductive type short circuit regions arranged at intervals below the substrate and adjacent to a collector region. The short circuit regions are located outside a first preset range having the center of a chip as a center, in a second preset range outside the first preset range and having the center of the chip as a center, in a third preset range outside the second preset range and having the center of the chip as a center, and in a range outside the third preset range and enclosed by a chip edge.

Provided is a power conversion device on which an IGBT power module that includes a main IGBT and a current sense IGBT in the same semiconductor chip is mounted, wherein the power conversion device is a high-performance and highly reliable power conversion device capable of accurately estimating a main current flowing through the main IGBT using a sense current in an entire operation region of the power conversion device. A power conversion device includes: a first IGBT through which a main current flows; a second IGBT which is disposed on the same semiconductor substrate as the first IGBT and through which a sense current flows; and a measurement device which calculates the main current based on the sense current, wherein the measurement device selects a method of calculating the main current corresponding to a current value of the sense current.

A packaged electronic device comprises a power semiconductor die that includes a first terminal and a second terminal, a power substrate comprising a dielectric substrate having a first metal cladding layer on an upper surface thereof, an encapsulation covering the power semiconductor die and at least a portion of the power substrate, a first lead extending through the encapsulation that is electrically connected to the first terminal, and a second lead extending through the encapsulation that is electrically connected to the second terminal. The first terminal is bonded to the first lead via a first transient liquid phase solder joint.

A method of manufacturing a semiconductor device having first and second main surfaces opposite to each other. The method includes: forming a first electrode at the first main surface of the semiconductor wafer; applying a first tape to the second main surface of the semiconductor wafer; forming roughness at a portion of a surface of the first tape; applying a second tape to an outer peripheral portion of the semiconductor wafer, so as to cover the portion of the surface of the first tape, with the roughness formed thereon, at the second main surface of the semiconductor wafer, to cover a portion of the first main surface of the semiconductor wafer, and to cover a side surface of the semiconductor wafer; heating the semiconductor wafer after the first and second tapes are applied; and subsequently forming a plated film at the surface of the first electrode by a plating treatment.

The present disclosure describes an insulated gate bipolar transistor and a manufacturing method thereof, and an electronic device. The insulated gate bipolar transistor comprises: a substrate of a first conductivity type; and a plurality of gate structures arranged at intervals in the substrate, each gate structure comprising a gate oxide layer, a first semiconductor doping layer, and a second semiconductor doping layer, the first semiconductor doping layer being provided on the second semiconductor doping layer, the gate oxide layer being provided on sidewalls of the first semiconductor doping layer, and a bottom portion and sidewalls of the second semiconductor doping layer, the first semiconductor doping layer having the first conductivity type, and the second semiconductor doping layer having a second conductivity type opposite to the first conductivity type.

A semiconductor device includes a semiconductor layer including an element region, and a termination region; a first electrode; a second electrode; a semi-insulating film located on the termination region; an insulating film located between the semiconductor layer and the semi-insulating film; and a protective film located on the semi-insulating film. The insulating film includes an inner perimeter portion, the inner perimeter portion being located between an end portion of the first electrode positioned at the termination region side and an end portion of the second semiconductor part positioned at the termination region side, an outer perimeter portion located between the second electrode and the semiconductor layer, and an intermediate portion located between the inner perimeter portion and the outer perimeter portion. A thickness of the intermediate portion is less than a thickness of the inner perimeter portion and a thickness of the outer perimeter portion.

A method of making an inverter comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

Provided is a semiconductor element including: a multilayer structure including: a conductive substrate; and an oxide semiconductor film arranged directly on the conductive substrate or over the conductive substrate via a different layer, the oxide semiconductor film including an oxide, as a major component, containing gallium, the conductive substrate having a larger area than the oxide semiconductor film.

Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate and p-type body regions are disposed at a top of the semiconductor substrate. The p-type body regions are in contact with an emitter metal layer. The semiconductor substrate includes at least one first region, and a region of the semiconductor substrate outside the at least one first region is a second region. Each of p-type body regions in the at least one first region is provided with a first p-type body region contact region, and the emitter metal layer is in contact with the first p-type body region contact region and forms an ohmic contact with the first p-type body region contact region. Each of p-type body regions in the second region forms no ohmic contact with the emitter metal layer.