A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.

In a semiconductor device, an element forming region formed with a semiconductor element for controlling a current is defined on a surface of a semiconductor substrate. A termination region is defined so as to surround the element forming region. In a gate electrode, a probe-contacting region and a wire region are defined. The probe-contacting region and the wire region are separated by an insulator formed on a surface of the gate electrode. Thus, the surface of the probe-contacting region and the surface of the wire region are located at the same height.

There are disclosed herein various implementations of a latch-up free power transistor. Such a device includes an insulated gate situated adjacent to a conduction channel in the power transistor, an emitter electrode in direct physical contact with the conduction channel, and a collector electrode in electrical contact with the conduction channel. The power transistor also includes an emitter layer in contact with a surface of a semiconductor substrate adjacent the conduction channel.

The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like.

A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.

This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed adjacent to the drift region and adjacent to the source region. The well region may include a channel region that has the second conductivity type disposed adjacent to the source region and proximal to a surface of the semiconductor device cell. The channel region may include a non-uniform edge that includes at least one protrusion.

A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided.

A semiconductor device manufacturing method according to an embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.

A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 m or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).