An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalls of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalls of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.

Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A source and drain region is positioned at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. The transistor includes a plurality of internal spacers, each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

The device disclosed herein includes, among other things, a substrate made of a first semiconductor material, at least one layer of insulating material positioned above the substrate, a fin structure positioned above the layer of insulating material and the substrate, the fin structure including first, second and third layers of semiconductor material, wherein the semiconductor materials of the first, second and third layers are different than the first semiconductor material, and a gate structure around a portion of the fin structure includes the first, second and third layers of semiconductor material.

An electronic circuit is disclosed. The electronic circuit includes a substrate having GaN, and a power switch formed on the substrate and including a first control gate and a first source. The electronic circuit also includes a drive circuit formed on the substrate and including an output coupled to the first control gate, and a power supply having a supply voltage and coupled to the drive circuit, where the output can be driven to the supply voltage.

A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern wherein the channel pattern includes semiconductor patterns vertically stacked and spaced apart from each other, the plurality of semiconductor patterns including a first semiconductor pattern and a neighboring second semiconductor pattern, and a gate electrode on the semiconductor patterns. The gate electrode includes an inner electrode between the first and second semiconductor patterns. The source/drain pattern includes a buffer layer and a main layer on the buffer layer. An indent region is defined in a vertical cross section of the device by the main layer, the first and second semiconductor patterns, and the inner electrode. The buffer layer is in the indent region. The buffer layer does not extend onto sidewalls of the first and second semiconductor patterns.

Various transistors, such as field-effect transistors, and methods of fabricating the transistors are disclosed herein. An exemplary transistor includes a phosphorene-containing layer having a channel region, a source region, and a drain region defined therein. A passivation layer is disposed over the phosphorene-containing layer. A source contact and a drain contact extend through the passivation layer, such that the source contact and the drain contact are respectively coupled with the source region and the drain region. A gate stack is disposed over the channel region. In some embodiments, the gate stack includes a gate dielectric layer and a gate electrode layer, where the gate dielectric layer extends through the passivation layer and contacts the channel region. In some embodiments, the gate stack includes a gate electrode layer disposed over the passivation layer, and a portion of the passivation layer serves as a gate dielectric layer of the gate stack.