A light-emitting device is provided. The light-emitting device includes a circuit board and a connection board disposed on the circuit board and having a first pad, a second pad, and a third pad. The light-emitting device also includes a first light-emitting element disposed on the connection board and having a first electrode and a second electrode and a second light-emitting element adjacent to the first light-emitting element and having a third electrode and a fourth electrode. The light-emitting device further includes a light-converting layer disposed on the first light-emitting element and the second light-emitting element. The thermal expansion coefficient of the connection board is smaller than the thermal expansion coefficient of the circuit board.

A display device may include: a substrate having a display area and a non-display area, and including a first surface and a second surface facing away from each other in a thickness direction of the substrate, and a side surface connecting the first and second surfaces; a light emitting element on the first surface of the substrate in the display area; a pad electrode on the first surface of the substrate in the non-display area; an intermediate electrode on the second surface of the substrate in the display area; and a side connection line on the side surface, and electrically connected to each of the pad electrode and the intermediate electrode. The pad electrode may include a first pad electrode and a second pad electrode. Opposite side surfaces of the second pad electrode may have the same inclination angles as opposite side surfaces of the first pad electrode.

A LED packaging module includes a plurality of LED chips, a wiring layer, and an encapsulant component. The LED chips are spaced apart, each of which includes chip first, chip second, and chip side surfaces, and an electrode unit. The wiring layer is disposed on the chip second surfaces, has first, second, and side wiring layer surfaces, and is divided into a plurality of wiring parts spaced apart. The first wiring layer surface contacts and is electrically connected to the electrode units. The encapsulant component includes first and second encapsulating layers, covers the chip side surfaces, the chip first surfaces, and the side wiring layer surface, and fills gaps among the wiring parts. Each LED chip has a thickness represented by T.sub.A, the first encapsulating layer has a thickness represented by T.sub.B, and T.sub.A and T.sub.B satisfy a relationship: T.sub.B/T.sub.A1.

A display device includes a first substrate having a first surface and a plurality of LED elements mounted on the first surface of the first substrate. Each of the plurality of LED elements includes a main body portion having a second surface facing the first surface of the first substrate and a third surface on a side opposite to the second surface, an anode electrode and a cathode electrode provided on the second surface of the main body portion, and an organic film bonded to the third surface of the main body portion. The organic film has a fourth surface facing and bonded to the third surface and a fifth surface on a side opposite to the fourth surface. The fifth surface of the organic film has a plurality of depressions.

A monolithic array chip comprises a first semiconductor layer; a common electrode located on the first semiconductor layer; a first light-emitting unit with a first electrode located on the first semiconductor layer; a second light-emitting unit with a second electrode located on the first semiconductor layer; a third light-emitting unit with a third electrode located on the first semiconductor layer, wherein the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are separated from each other by a trench.

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.

A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.

A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor substrate, etching an epitaxial layer, depositing a conductive material, depositing an insulation passivation layer and etching through the insulation passivation layer.

A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.