A semiconductor device includes a vertical MOS transistor with a plurality of parallel RESURF drain trenches separated by a constant spacing in a vertical drain drift region. The vertical MOS transistor has chamfered corners; each chamfered corner extends across at least five of the drain trenches. A RESURF termination trench surrounds the drain trenches, separated from sides and ends of the drain trenches by distances which are functions of the drain trench spacing. At the chamfered corners, the termination trench includes external corners which extend around an end of a drain trench which extends past an adjacent drain trench, and includes internal corners which extend past an end of a drain trench which is recessed from an adjacent drain trench. The termination trench is separated from the drain trenches at the chamfered corners by distances which are also functions of the drain trench spacing.

A power semiconductor device and a method of manufacturing a power semiconductor device is provided, including a shield gate trench (SGT) metal-oxide semiconductor field-effect transistor (MOSFET). The present disclosure provides for a MOSFET with a reduced charge between the gate conductive region and the drain or collector region, in order to improve the switching efficiency of the MOSFET.

A semiconductor device includes a current spreading layer, a gate trench, a gate electrode, a first body region, a first source region, a second body region and a second source region. The first body region is beneath and in contact with the gate trench. The first source region is formed in the first body region. The second body region extends from a first surface of the current spreading layer into the current spreading layer and adjoins a first sidewall of the gate trench. The second source region is formed in the second body region and adjoins the first sidewall of the gate trench.

Vertical semiconductor devices with deep wells and associated fabrication methods are disclosed herein. A disclosed process for forming a semiconductor device includes forming, on a drift region having a first conductivity type, a deep well region for the semiconductor device. The deep well region can be formed by an implant. The deep well region has a second conductivity type. The deep well region of the second conductivity type leaves a portion of the surface of the drift region exposed. The process also includes epitaxially forming a semiconductor region that extends from the surface of the drift region to above the deep well region for the semiconductor device. The semiconductor region can be used as at least a part of the main operational current path of the semiconductor device when the semiconductor device is finished and is devoid of implant damage from the implant.

First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

A method for producing a semiconductor component includes providing a semiconductor body having a first semiconductor material extending to a first surface and at least one trench, the at least one trench extending from the first surface into the semiconductor body, a first insulation layer being arranged in the at least one trench. The method further includes forming a second insulation layer on the first surface having a recess that overlaps in a projection onto the first surface with the at least one trench, forming a mask region in the recess, etching the second insulation layer selectively to the mask region, depositing a third insulation layer over the first surface, and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the at least one trench is exposed at the first surface.

A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

A method of manufacturing a semiconductor device includes: forming a first trench in a first area of a drift layer that has a surface including the first area and a second area; growing a crystal of a p-type base layer on a surface of the drift layer after forming the first trench; and growing a crystal of an n-type source layer on a surface of the base layer. Material of the drift layer, the base layer, and the source layer are a wide-gap semiconductor.

A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor.

Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.