A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate insulating layer, a fourth semiconductor region of the second conductivity type, a first conductive unit and a first insulating layer. The fourth semiconductor region is provided selectively on the first semiconductor region. The fourth semiconductor region is separated from the second semiconductor region. At least a portion of the first conductive unit is surrounded with the fourth semiconductor region. At least a portion of the first insulating layer is provided between the first conductive unit and the fourth semiconductor region. A thickness of a portion of the first insulating layer is thinner than a film thickness of the gate insulating layer.

A voltage-controlled switching device includes a drain/drift structure formed in a semiconductor portion with a lateral cross-sectional area A.sub.Q, a source/emitter terminal, and an emitter channel region between the drain/drift structure and the source/emitter terminal. A resistive path electrically connects the source/emitter terminal and the emitter channel region. The resistive path has an electrical resistance of at least 0.1 m*cm.sup.2/A.sub.Q.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.

In an embodiment, a semiconductor device includes a semiconductor body having a first major surface, a second major surface opposing the first major surface and at least one transistor device structure, a source pad and a gate pad arranged on the first major surface, a drain pad and at least one further contact pad coupled to a further device structure. The drain pad and the at least one further contact pad are arranged on the second major surface.

A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a source in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure comprising a body ring structure in the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure.

A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.