The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer is disposed on the buried oxide layer. A first well is disposed in the semiconductor layer. A second well and a third well are disposed to opposite sides of the first well and separated from the first well. An isolation feature covers the first well and the third well. A poly field plate is disposed on the isolation feature and over the semiconductor layer between the first well and the third well. A first anode doped region is disposed on the second well. A second anode doped region and a third anode doped region are disposed on the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.

A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame trench, an edge termination structure comprising a glass structure, forming a conductive layer on the semiconductor substrate and the edge termination structure, and removing a portion of the conductive layer above the edge termination structure. A remnant portion of the conductive layer forms a conductive structure that covers a portion of the edge termination structure directly adjoining a sidewall of the frame trench.

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

A semiconductor device includes a first load terminal at a first surface of a semiconductor body and a second load terminal at the opposing surface. An active device area is surrounded by an edge termination area. Load terminal contacts are absent in the edge termination area and are electrically connected to the semiconductor body in the active device area at the first surface. A positive temperature coefficient structure is between at least one of the first and second load terminals and a corresponding one of the first and second surfaces. Above a maximum operation temperature specified for the semiconductor device, a specific resistance of the positive temperature coefficient structure increases by at least two orders of magnitude within a temperature range of at most 50 K. A degree of area coverage of the positive temperature coefficient structure is greater in the edge termination area than in the active device area.

Impurity elements are doped at a high concentration exceeding a thermodynamic equilibrium concentration into a solid material having an extremely small diffusion coefficient of the impurity element. A method for doping impurities includes steps for depositing source film made of material containing impurity elements with a film thickness on a surface of a solid target object (semiconductor substrate) made from the solid material. The film thickness is determined in consideration of irradiation time per light pulse and the energy density of the light pulse. The method also includes a step for irradiating the source film by the light pulse with the irradiation time and the energy density so as to dope the impurity elements into the target object at a concentration exceeding a thermodynamic equilibrium concentration.

A method of fabricating a diode includes forming a first semiconductor layer having a first portion and a second portion extending from the first portion on a substrate; forming first and second electrodes on the substrate, the first electrode extending over and being in contact with the first portion of the first semiconductor layer; forming an insulting film to cover the first electrode and the first portion of the first semiconductor layer; and forming a second semiconductor layer having a first portion and a second portion extending from the first portion on the substrate. The second portion of the second semiconductor layer overlapping with the second portion of the first semiconductor layer to define a vertically stacked heterojunction therewith. The first portion of the second semiconductor layer extending over and being in contact with the second electrode. Each of the first and second semiconductor layers includes an atomically thin semiconductor.

Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

A semiconductor device includes a semiconductor body having opposite first and second surfaces, a drift or base zone in the semiconductor body and an oxygen diffusion barrier in the semiconductor body. The drift or base zone is located between the first surface and the oxygen diffusion barrier and directly adjoins the oxygen diffusion barrier. The semiconductor device further includes first and second load terminal contacts. At least one of the first and the second load terminal contacts is electrically connected to the semiconductor body through the first surface.

A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously.

A semiconductor device is provided that can prevent a current from being concentrated into a specific chip, and can reduce loss as well as noise. The semiconductor device according to the present invention includes: a switching element; a main diode that is connected in parallel to the switching element; and an auxiliary diode that is connected in parallel to the switching element and has a different structure from that of the main diode, wherein in a conductive state a current flowing through the auxiliary diode is smaller than that through the main diode, and in a transition period from the conductive state to a non-conductive state a current flowing through the auxiliary diode is larger than that through the main diode.