There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening.

A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.

A semiconductor device is provide that includes: a semiconductor body having a first surface, an inner region, and an edge region; a pn junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region; a recess extending from the first surface in the edge region into the semiconductor body, the recess comprising at least one sidewall; a dielectric filling the recess. In the dielectric, a dielectric number, in the lateral direction, decreases as a distance from the first sidewall increases.

A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty.

A silicon carbide semiconductor device includes an impurity region including a p type impurity and disposed within a silicon carbide layer to surround an element region as seen in plan view. The impurity region has a peak concentration of the p type impurity at a position within the silicon carbide layer distant from a first main surface. The peak concentration is not less than 110.sup.16 cm.sup.3 and not more than 510.sup.17 cm.sup.3. The impurity region is formed by implanting ions of the p type impurity into the silicon carbide layer. Then, a silicon dioxide film is formed to cover the first main surface of the silicon carbide layer by performing a thermal oxidation process on the silicon carbide layer, and the concentration of the p type impurity in the vicinity of the first main surface is lowered.

A semiconductor device includes: a semiconductor substrate; a device region on the semiconductor substrate; a planar edge termination region on the semiconductor substrate to surround the device region; and a passivation film covering the edge termination region, wherein the passivation film includes a semi-insulating film directly contacting the semiconductor substrate.

A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.

A semiconductor device has an active region through which a main current flows, a gate ring region surrounding a periphery of the active region, a source ring region surrounding a periphery of the gate ring region, and a termination region surrounding a periphery of the source ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and further, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film, a first first-electrode, a first plating film, and a second electrode. The semiconductor device has, in the source ring region, a second first-electrode provided at a surface of the second semiconductor layer, and a second plating film provided on the second first-electrode.

A method of manufacturing a semiconductor device, including preparing a semiconductor substrate having a main surface, forming a device element structure on the main surface, forming a protective film on the main surface of the semiconductor substrate to protect the device element structure, the protective film having an opening therein, forming at least one material film in a predetermined pattern on the main surface of the semiconductor substrate and in the opening of the protective film, the at least one material film being separate from the protective film by a distance of less than 1 mm, forming a resist film on the main surface of the semiconductor substrate, covering the protective film and the at least one material film, the resist film having an opening therein corresponding to an inducing region for impurity defects, and inducing the impurity defects in the semiconductor substrate, using the resist film as a mask.