A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of In.sub.x1Al.sub.y1Ga.sub.1-x1-y1N (0x1<1, 0y1<1, 0<1x1y1<1) and provided on the electron transit layer; a source electrode and a drain electrode that are provided on the electron supply layer and located apart from each other; a threshold voltage adjustment layer constituted of In.sub.x2Al.sub.y2Ga.sub.1-x2-y2N (0x2<1, 0y2<1, 0<1x2y21) of a p-type and provided on a part of the electron supply layer located between the source electrode and the drain electrode; and a gate electrode provided on the threshold voltage adjustment layer. A high resistance layer is respectively interposed both between the gate electrode and the threshold voltage adjustment layer, and between the threshold voltage adjustment layer and the electron supply layer.

A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H.sub.0; a second semiconductor layer having a conduction band minimum E.sub.C2; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level H.sub.0 below the conduction band minimum E.sub.c2 for zero bias applied to the gate metal layer and to obtain n-terminal characteristics.

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the method includes depositing alternating insulating and electrode layers on a substrate to form a multi-layer film. The method further includes etching the film to the substrate to form through-holes, each of which defines a channel region. The method further includes depositing barrier, storage, and tunnel layers in sequence on inner walls of through-holes to form gate stacks. The method further includes depositing and incompletely filling a channel material on a surface of the tunnel layer of gate stacks to form a hollow channels. The method further includes forming drains in contact hole regions for bit-line connection in top portions of the hollow channels. The method further includes forming sources in contact regions between the through-holes and the substrate in bottom portions of the hollow channels.

A semiconductor device includes a fin having a first semiconductor material. The fin includes a source/drain (S/D) region and a channel region. The S/D region provides a top surface and two sidewall surfaces. A width of the S/D region is smaller than a width of the channel region. The semiconductor device further includes a semiconductor film over the S/D region and having a doped second semiconductor material. The semiconductor film provides a top surface and two sidewall surfaces that are substantially parallel to the top and two sidewall surfaces of the S/D region respectively. The semiconductor device further includes a metal contact over the top and two sidewall surfaces of the semiconductor film and operable to electrically communicate with the S/D region.

A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.

A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.

FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, forming a buffer layer on the semiconductor substrate by filling the trenches and covering the semiconductor substrate, and forming a fin body by etching the buffer layer. The FinFET fabrication method may further includes forming a insulation layer on the buffer layer around the fin body; forming a channel layer on the surface of the fin body; forming a gate structure across the fin body; forming source/drain regions in the channel layer on two sides of the gate structure; and forming an electrode layer on the source/drain regions.

Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.