Embodiments of the invention provide methods for forming III-V gate-all-around field effect transistors on silicon substrates that utilize Aspect-Ratio Trapping to reduce or eliminate dislocation defects associated with lattice mismatches. A field dielectric material defining a trench is formed on a crystalline silicon substrate. A channel feature comprising III-V material is subsequently formed inside the trench. Source/drain features are then formed at both ends of the channel feature inside the trench. Lastly, gate dielectric layers and a gate feature are formed surrounding a portion of the channel feature.

A high frequency semiconductor device includes a stacked body, a gate electrode, a source electrode and a drain electrode. The gate electrode includes a bending gate part and a straight gate part. The bending gate part is extended in a zigzag shape and has first and second outer edges. The source electrode includes a bending source part and a straight source part. The bending source part has an outer edge spaced by a first distance from the first outer edge of the bending gate part along a normal direction. The drain electrode includes a bending drain part and a straight drain part. The bending drain part has an outer edge spaced by a second distance from the second outer edge of the bending gate part along the normal direction.

A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.

The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a collector; a base region above the collector; an emitter laterally connecting to the base region; and an extrinsic base connecting to the base region.

A method includes epitaxially growing a gallium nitride (GaN) layer over a silicon substrate. The method further includes epitaxially growing a donor-supply layer over the GaN layer. The method further includes forming a source and a drain on the donor-supply layer. The method further includes forming a gate structure between the source and the drain on the donor-supply layer. The method further includes plasma etching a portion of a drift region of the donor-supply layer to a depth of less than 60% of a donor-supply layer thickness. The method further includes depositing a dielectric layer over the donor-supply layer.

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10.sup.8 cm.sup.2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

A compound semiconductor device is disclosed. The compound semiconductor device comprises a substrate having at least a first doped region and at least a second doped region; a semiconductor layer disposed on the substrate; and a buffer layer located between said substrate and said semiconductor layer; wherein doping conditions of said first doped region and said second doped region are different from each other; wherein said semiconductor layer has different thicknesses on locations corresponding to said first doped region and said second doped region respectively, and is formed as a structure with difference in thickness.

A field effect transistor includes a trench in a field dielectric material on a crystalline silicon substrate and source/drain features inside the trench. The field effect transistor further includes a channel feature comprising a III-V material in the trench and spanning between the source/drain features, and gate dielectric layers and a gate feature surrounding a portion of the channel feature.

The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode.