Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

An electronic device can transistor having a channel layer that includes a compound semiconductor material. In an embodiment, the channel layer overlies a semiconductor layer that includes a carrier barrier region and a carrier accumulation region. The charge barrier region can help to reduce the likelihood that de-trapped carriers from the channel layer will enter the charge barrier region, and the charge accumulation region can help to repel carriers in the channel layer away from the charge barrier layer. In another embodiment, a barrier layer overlies the channel layer. Embodiments described herein may help to produce lower dynamic on-resistance, lower leakage current, another beneficial effect, or any combination thereof.

A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of In.sub.x1Al.sub.y1Ga.sub.1-x1-y1N (0x1<1, 0y1<1, 0<1x1y1<1) and provided on the electron transit layer; a source electrode and a drain electrode that are provided on the electron supply layer and located apart from each other; a threshold voltage adjustment layer constituted of In.sub.x2Al.sub.y2Ga.sub.1-x2-y2N (0x2<1, 0y2<1, 0<1x2y21) of a p-type and provided on a part of the electron supply layer located between the source electrode and the drain electrode; and a gate electrode provided on the threshold voltage adjustment layer. A high resistance layer is respectively interposed both between the gate electrode and the threshold voltage adjustment layer, and between the threshold voltage adjustment layer and the electron supply layer.

Thin film transistors (TFTs), including radiofrequency TFTs, with submicron-scale channel lengths and methods for making the TFTs are provided. The transistors include a trench cut into the layer of semiconductor that makes up the body of the transistors. Trench separates the source and drain regions and determines the channel length of the transistor.

Transition metal dichalcogenide (TMD)-based spintronics devices, each including a TMD thin film layer, a first gate electrode, a first insulating layer sandwiched between the TMD thin film layer and the first gate electrode, a second gate electrode, and a second insulating layer sandwiched between the TMD thin film layer and the second gate electrode. Such a device, when also including a source electrode and a drain electrode, functions as a spin filter. On the other hand, when also including one source electrode and two drain electrode terminals, such a device functions as a spin separator. Also disclosed are methods of using the above-described TMD-based spintronics devices.

A two-dimensional (2D) heterojunction interlayer tunneling field effect transistor (Thin-TFET) allows for particle tunneling in a vertical stack comprising monolayers of two-dimensional semiconductors separated by an interlayer. In some examples, the two 2D materials may be misaligned so as to influence the magnitude of the tunneling current, but have a modest impact on gate voltage dependence. The Thin-TFET can achieve very steep subthreshold swing, whose lower limit is ultimately set by the band tails in the energy gaps of the 2D materials produced by energy broadening. These qualities in turn make the Thin-TFET an ideal low voltage, low energy solid state electronic switch.

An embodiment is a structure including a first active device in a first region of a substrate, the first active device including a first layer of a two-dimensional (2-D) material, the first layer having a first thickness, and a second active device in a second region of the substrate, the second active device including a second layer of the 2-D material, the second layer having a second thickness, the 2-D material including a transition metal dichalcogenide (TMD), the second thickness being different than the first thickness.

A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS.sub.2, WS.sub.2, WSe.sub.2, and/or combinations thereof.

An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.