An integrated circuit device including a substrate including a word line trench and a first recess adjacent to a first side wall portion of an inner wall of the word line trench, a channel region on the inner wall and extending in a first direction parallel to an upper surface of the substrate, the channel region including a first channel region in a portion of the substrate adjacent to the inner wall and a second channel region on the inner wall and including a two-dimensional (2D) material of a first conductivity type, a gate insulating layer on the second channel region, a word line on the gate insulating layer and inside the word line trench, and a source region in a first recess and including the 2D material of the first conductivity type may be provided.

A semiconductor device may include a transistor structure. The transistor structure may include a metal structure extending along a vertical direction; a gate dielectric layer around the metal structure; a channel layer around the gate dielectric layer; a first metal electrode disposed below the metal structure and in electrical contact with a first end of the channel layer; a second metal electrode disposed above the metal structure and in electrical contact with a second end of the channel layer; and a third metal electrode disposed above and in electrical contact with the metal structure.

A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.

Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type which is provided above the substrate; a second nitride semiconductor layer which is provided above the first nitride semiconductor layer; an electron transport layer and an electron supply layer which are sequentially provided above the second nitride semiconductor layer; a third nitride semiconductor layer and a gate electrode which are sequentially provided above the electron supply layer; a source electrode; and a drain electrode, the second nitride semiconductor layer includes: a current conducting portion of the first conductivity type which is located below the third nitride semiconductor layer and includes a first impurity; and a current blocking portion which is provided about the current conducting portion, and the concentration of the first impurity in the electron transport layer is lower than the concentration of the first impurity in the current conducting portion.

A nitride semiconductor device includes a substrate, a first nitride semiconductor layer, a first p-type nitride semiconductor layer and a second nitride semiconductor layer disposed sequentially from below; an electron transport layer and an electron supply layer arranged sequentially from below to cover a first opening and the second nitride semiconductor layer, the first opening penetrating through the second nitride semiconductor layer and the first p-type nitride semiconductor layer; a second p-type nitride semiconductor layer or an insulating layer disposed in a position overlapping with a bottom surface of the first opening; a gate electrode disposed in a position overlapping with the second nitride semiconductor layer; a first source electrode disposed to cover a second opening penetrating through the electron supply layer and the electron transport layer; a drain electrode; and a second source electrode disposed above the second p-type nitride semiconductor layer or the insulating layer.

A semiconductor device includes a substrate; a gallium nitride layer located on a non-polar surface of the substrate, the gallium nitride layer including a plurality of fin parts separated from each other in a first direction parallel to a c-axis direction, the plurality of fin parts extending in a second direction; an electron supply layer located at a Ga-surface of at least one of the fin parts; a source finger part extending in the first direction and contacting the electron supply layer; a drain finger part extending in the first direction and contacting the electron supply layer, the drain finger part being separated from the source finger part in the second direction; and a gate electrode positioned between the source finger part and the drain finger part, the gate electrode facing the electron supply layer in the first direction.

The folded channel gallium nitride based field-effect transistor includes: a base layer; a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region; a source electrode and a drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.