Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

In one embodiment, a semiconductor device includes a substrate, and interconnects provided above the substrate. The device further includes a first insulator that is provided on the interconnects and on air gaps provided between the interconnects, surrounds the interconnects from lateral sides of the interconnects, and is formed of a first insulating material. The device further includes a second insulator that surrounds an interconnect region including the interconnects and the air gaps from the lateral sides of the interconnects through the first insulator, and is formed of a second insulating material different from the first insulating material.

The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.

A method of forming a vertical transistor includes forming at least one fin on stacked layers. The stacked layers include a substrate, a doped silicon layer, and an intrinsic layer interposed between the pair of fins and the substrate. The method further includes forming a spacer hardmask over the pair of fins, and forming a bottom spacer. Forming the bottom spacer includes selective oxidation of the SiGe layer.

A semiconductor device including a memory cell is provided. The memory cell comprises a transistor, a memory element and a capacitor. One of first and second electrodes of the memory element and one of first and second electrodes of the capacitor are formed by a same metal film. The metal film functioning as the one of first and second electrodes of the memory element and the one of first and second electrodes of the capacitor is overlapped with a film functioning as the other of first and second electrodes of the capacitor.

In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

A semiconductor structure including a stacked FinFET fuse is provided in which the stacked FinFET fuse includes a plurality of vertically stacked and spaced apart conductive semiconductor fin portions and a doped epitaxial semiconductor material structure located on exposed surfaces of each conductive semiconductor fin portion of the vertical stack. In the FinFET fuse, a topmost surface of a bottom doped epitaxial semiconductor material structure is merged to a bottommost surface of an overlying doped epitaxial semiconductor material structure.

A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.

A semiconductor structure includes first and second transistors each having a source terminal, a drain terminal, and a gate terminal. The semiconductor structure further includes a program line; a first metal plate over the first and the second transistors; a first insulator over the first metal plate; a second metal plate over the first insulator; a second insulator over the second metal plate; and a third metal plate over the second insulator. The first metal plate, the first insulator, and the second metal plate form a first anti-fuse element. The second metal plate, the second insulator, and the third metal plate form a second anti-fuse element. The source terminal of the first transistor is electrically connected to the first metal plate. The source terminal of the second transistor is electrically connected to the third metal plate. The program line is electrically connected to the second metal plate.

Disclosed are devices and methods having a programmable resistor and an on-package decoupling capacitor (OPD). In one aspect a package includes an OPD and a programmable resistor formed from at least one thin-film transistor (TFT). The programmable resistor is disposed in series with the OPD between a supply voltage (VDD) conductor and a ground conductor.