Photodetector structures and methods of manufacture are provided. The method includes forming undercuts about detector material formed on a substrate. The method further includes encapsulating the detector to form airgaps from the undercuts. The method further includes annealing the detector material causing expansion of the detector material into the airgaps.

Systems and methods may be provided for fabricating infrared focal plane arrays. The methods include providing a device wafer, applying a coating to the device wafer, mounting the device wafer to a first carrier wafer, thinning the device wafer while the device wafer is mounted to the first carrier wafer, releasing the device wafer from the first carrier wafer, singulating the device wafer into individual dies, each die having an infrared focal plane array, and hybridizing the individual dies to a read out integrated circuit.

An image sensor with an array of pixels is provided. The array may include a semiconductor substrate having opposing first and second sides. A first photodiode region may be implanted in the semiconductor substrate through the first side. A second photodiode region may be implanted in the semiconductor substrate through the second side. The second photodiode region may be implanted to overlap with the first photodiode region in the semiconductor substrate to form a continuous photodiode region that extends from the first side to the second side of the substrate. The continuous region may generate charge in response to image light. The continuous region may belong to a single pixel that generates an image signal from the charge. The image signal may be conveyed to readout circuitry via metallization layers formed over the substrate. The first and second photodiode regions may be thermally activated prior to forming the metallization layers.

An embodiment isolation structure includes a first passivation layer over a bottom surface and extending along sidewalls of a trench in a semiconductor substrate, wherein the first passivation layer includes a first dielectric material. The semiconductor device further includes a passivation oxide layer in the trench on the first passivation layer, wherein the passivation oxide layer includes an oxide of the first dielectric material and has a higher atomic percentage of oxygen than the first passivation layer, The semiconductor device further includes a second passivation layer in the trench on the passivation oxide layer, wherein the second passivation layer also includes the first dielectric material and has a lower atomic percentage of oxygen than the passivation oxide layer.

A method of manufacturing a solid-state image sensor, includes forming a first isolation region of a first conductivity type in a semiconductor layer having first and second surfaces, the forming the first isolation region including first implantation for implanting ions into the semiconductor layer through the first surface, forming charge accumulation regions of a second conductivity type in the semiconductor layer, performing first annealing, forming an interconnection on a side of the first surface of the semiconductor layer after the first annealing, and forming a second isolation region of the first conductivity type in the semiconductor layer, the forming the second isolation region including second implantation for implanting ions into the semiconductor layer through the second surface. The first and second isolation regions are arranged between the adjacent charge accumulation regions.

A method for producing an image pickup apparatus includes: a process of cutting an image pickup chip substrate where electrode pads are formed around each of the light receiving sections to fabricate image pickup chips; a process of bonding image pickup chips determined as non-defective products to a glass wafer to fabricate a joined wafer; a process of filling a sealing member among the image pickup chips on the joined wafer; a machining process including a thinning a thickness of the joined wafer to flatten a machining surface and a forming through-hole interconnections, each of which is connected to each of the electrode pads; a process of forming a plurality of external connection electrodes, each of which is connected to each of the electrode pads via each of the through-hole interconnections; and a process of cutting the joined wafer.

A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.

An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n.sup.-type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n.sup.-type semiconductor region, and a p.sup.-type semiconductor region formed between the n.sup.-type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n.sup.-type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p.sup.-type semiconductor region is lower than a net impurity concentration in the p-type well.

Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.

Photodetector structures and methods of manufacture are provided. The method includes forming undercuts about detector material formed on a substrate. The method further includes encapsulating the detector to form airgaps from the undercuts. The method further includes annealing the detector material causing expansion of the detector material into the airgaps.