A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

A single photon avalanche diode includes a semiconductor substrate doped with a first conductivity type and having a first face and a second face opposite to the first face; a peripheral isolation structure delimiting an active region of the semiconductor substrate, the peripheral isolation structure extending into the semiconductor substrate from the first face towards the second face; a semiconductor region doped with a second conductivity type opposite to the first conductivity type, extending into the active region of the semiconductor substrate from the first face towards the second face; and a capacitive effect passivation structure disposed inside a first trench which extends into the semiconductor region, the capacitive effect passivation structure extending in contact with the semiconductor region and being configured to form a first electric charge accumulation layer in the semiconductor region at the interface with the first trench.

The present description concerns an electronic circuit manufacturing method comprising, in the order, forming an opening in a semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to the first surface, the opening positioned between the first surface and the second surface and forming an electrically-conductive pad, the electrically-conductive pad including a first portion positioned over the first surface and a second portion covering the flanks of the opening and delimiting a gap in the opening, and depositing a first layer covering the electrically-conductive pad and filling the gap, the first layer containing a first resin, the first resin being non-photosensitive, and crosslinking the first resin in the first layer, and chemically etching by plasma the first layer to delimit a first block of the first resin in the gap, and depositing a first protection layer on the first block.

A semiconductor device, a back-side deep trench isolation (BDTI) structure of a semiconductor device, and method of manufacturing a semiconductor structure are provided. The semiconductor device, comprising: a pixel region disposed within a substrate and comprising an image sensing element configured to convert electromagnetic radiation into an electrical signal; and one or more BDTI structures extending from a first-side of the substrate to positions within the substrate; wherein the one or more of BDTI structures comprise one or more ferroelectric materials.

In an imaging device, the device is reduced in size and height without deteriorating the imaging capability of an imaging element. An imaging device includes: an imaging element having a pixel region and a peripheral region on the front side, the pixel region including multiple pixels, the peripheral region surrounding the pixel region; a rewiring layer that is provided on the front side of the imaging element and has an opening formed through a region including the pixel region; a sealing resin portion that is made of a sealing resin material and is provided to cover a portion around the imaging element and the back side of the rewiring layer; and a connecting portion that is provided on the peripheral region of the imaging element and electrically connects the imaging element and the rewiring layer.

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region comprising a first dopant having a first doping type. A deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a second dopant having a second doping type opposite the first doping type. An isolation structure is disposed within the semiconductor substrate. The isolation structure extends from the back-side surface of the semiconductor substrate to a point below the back-side surface. A doped liner is disposed between the isolation structure and the second doped region. The doped liner comprises the second dopant.

A photosensitive chip, a manufacturing method thereof, and a photosensitive module are provided. The photosensitive chip includes an isosceles trapezoid body, a positive electrode, and a negative electrode. The isosceles trapezoid body comprises an N-type semiconductor layer and a P-type semiconductor layer. The P-type semiconductor layer is disposed adjacent to the N-type semiconductor layer. The positive electrode is electrically connected to the P-type semiconductor layer, and the negative electrode is electrically connected to the N-type semiconductor layer.

A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.

An image sensor device may include one or more types of antireflection structures on a metal grid surrounding the pixel sensors in a pixel sensor array of the image sensor device. The antireflection structures may include an antireflective layer, nanostructures extending from the antireflective layer, and/or a plurality of cavities formed in the metal grid structure. The antireflection structures may be included in and/or on one or more surfaces of the metal grid structure to reduce the reflection of incident light, which may reduce the likelihood and/or magnitude of optical crosstalk between adjacent pixel sensors in the pixel sensor array.

A method of producing an epitaxial silicon wafer includes irradiating a surface of a silicon wafer with a beam of cluster ions containing SiH.sub.x ions (at least one of the integers 1 to 3 is selected as x of the SiH.sub.x ions) and C.sub.2H.sub.y ions (at least one of the integers 2 to 5 is selected as y of the C.sub.2H.sub.y ions) to form a modified layer that is located in a surface layer portion of the silicon wafer and that contains as a solid solution of the constituent elements of the cluster ion beam, and further includes forming a silicon epitaxial layer on the modified layer of the silicon wafer. The dose of the SiH.sub.x ions is 1.510.sup.14 ions/cm.sup.2 or more.