An imaging device includes: a semiconductor substrate; pixels arranged two-dimensionally along row and column directions on the substrate; and one or more interconnection layers located on the semiconductor substrate, including a first signal line extending along the column direction and a second signal line to which a multi-level signal is applied. A first pixel includes: a photoelectric converter; a charge storage region; a first interconnection electrically connected to the charge storage region; and a first transistor that includes a first diffusion layer electrically connected to the first signal line and a second diffusion layer electrically connected to the second signal line and that outputs a signal to the first signal line. The first and second signal lines and the first interconnection are arranged in a first interconnection layer. The second signal line is located between the first interconnection and the first signal line, viewed perpendicularly to the substrate.

A circuit for correlated double sampling is disclosed. In one aspect, the circuit comprises a reset switch connected with an input node, and with a first node of a first capacitor; a sampling switch connected with the input node, and with a first node of a second capacitor; a second node of the first/second capacitor is adapted to be connected with a first/second reference node, of which at least one using a reference switch; a first switch connected between the second node of the first capacitor and the first node of the second capacitor; a second switch connected between the first node of the first capacitor and the second node of the second capacitor.

A unit pixel includes first and second photoelectric conversion units, a first transfer transistor disposed between the first photoelectric conversion unit and a first node, a first capacitor connected to the first node through a first switch transistor, and a second transfer transistor disposed between the second photoelectric conversion unit and the first node. A signal including a first voltage level is applied to the first transfer transistor and the second transfer transistor during a first time interval, a signal including a second voltage level is applied to the first transfer transistor, the second transfer transistor, and the first switch transistor during a second time interval, a signal including a third voltage level is applied to the first transfer transistor during a third time interval, and the signal including the first voltage level is applied to the second transfer transistor and the first switch transistor during a fourth time interval.

A solid-state imaging element of the present disclosure has arranged inside a pixel: a charge accumulation unit that accumulates a charge photoelectrically converted by a photoelectric conversion unit; a reset transistor that selectively applies a reset voltage to the charge accumulation unit; an amplification transistor having a gate electrode being electrically connected to the charge accumulation unit; and a selection transistor connected in series to the amplification transistor. Additionally, the solid-state imaging element includes: first wiring electrically connecting the charge accumulation unit and the gate electrode of the amplification transistor; second wiring electrically connected to a common connection node of the amplification transistor and the selection transistor and formed along the first wiring; and third wiring electrically connecting the amplification transistor and the selection transistor.

A capacitive trans-impedance amplifier (CTIA) unit cell includes a CTIA and a clamp capacitor. The CTIA is configured to process a first electrical charge induced by a photocurrent. The clamp capacitor includes a first clamp terminal configured to receive a dynamic signal and a second clamp terminal connected to a CTIA output of the CTIA so as to establish an integrating node. The clamp capacitor delivers a second electrical charge to the CTIA in response to receiving the dynamic signal so as to adjust an integrating reset level at the integrating node.

An electronic device and a control method are provided. The electronic device includes a sensing pixel. The sensing pixel includes a photosensitive element, a first transistor, a second transistor and a third transistor. The first transistor is coupled to the photosensitive element and for receiving a reset signal. The second transistor is coupled to the photosensitive element. The third transistor is coupled to the second transistor and for receiving a scan signal. During a reset period, a reset signal waveform of the reset signal and a first scan signal waveform of the scan signal are at least partially overlapped.

A pixel is included, the pixel including a photoelectric conversion portion configured to convert incident light to a charge by photoelectric conversion and accumulate the charge, a charge transfer unit configured to transfer the charge generated in the photoelectric conversion portion, a diffusion layer to which the charge is transferred through the charge transfer unit, the diffusion layer having a predetermined storage capacitance, a conversion unit configured to convert the charge transferred to the diffusion layer to a pixel signal, and connection wiring configured to connect the diffusion layer and the conversion unit. The connection wiring is connected to the diffusion layer and the conversion unit through contact wiring extending in a vertical direction with respect to a semiconductor substrate on which the diffusion layer is formed and is formed closer to the semiconductor substrate than other wiring provided in the pixel.

A pixel array within an integrated-circuit image sensor includes four sets of photodetection elements disposed in respective pixel-array regions having a shared corner, four readout circuits each coupled to a respective one of the four sets of photodetection elements, a reset node, a reset transistor, and binning transistors. Each of the four readout circuits has a floating diffusion node, a first transfer gate coupled between the floating diffusion node and a constituent photodetection element of the respective one of the four sets of photodetection elements, and an amplifier transistor having a gate terminal coupled to the floating diffusion node. The reset transistor is coupled between the reset node and a reset-voltage supply, and each one of the binning transistors is coupled between the reset node and the floating diffusion node of a respective one of the readout circuits.

According to the present invention there is provided a vision sensor comprising, an array of pixels comprising rows and columns of pixels, wherein each pixel in the array comprises, a photosensor which is configured to output a current proportional to the intensity of light which is incident on the photosensor; a current source which is configured such that it can output a current which has a constant current level which is equal to the current level of the current output by the photosensor at a selected first instant in time, and can maintain that constant current level even if the level of the current output from the photosensor changes after said selected first instant in time; an integrator which is configured to integrate the difference between the level of current output by the current source and the level of current output by the photosensor, after the selected first instant in time; wherein the vision sensor further comprises a counter which can measure time, wherein the counter is configured such that it can begin to measure time at the selected first instant; and wherein each pixel in the array further comprises a storage means which can store the value on the counter at a second instant in time, the second instant in time being the instant when the integration of the difference between the level of current output by the current source and the level of current output by the photosensor of that pixel reaches a predefined threshold level. There is further provided a corresponding method of vision sensing, and a depth sensor assembly which comprises the vision sensor.

An imaging device that includes pixels arranged in a matrix having rows and columns, the pixels including first pixels and second pixels different from the first pixels, the first pixels and the second pixels being located in one of the columns, each of the pixels including a photoelectric converter that converts incident light into signal charge, and a first transistor having a first gate, a first source and a first drain, the first gate being coupled to the photoelectric converter. The imaging device further includes a first line coupled to one of the first source and drain of the first pixels; a second line coupled to one of the first source and drain of the second pixels; a third line coupled to the other of the first source and drain of the first pixels; and voltage circuitry coupled to the third line and that supplies a first and second voltage.