A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

The short-circuit protection circuit for a Gate Driver on Array (GOA) liquid crystal panel contains a power module, a first booster module, a feedback module, and a second booster module series-connected in the this order. A control module is electrically connected to the first booster, feedback, and second booster modules. The power module provides a power voltage. The control module provides a pulse width modulation (PWM) signal so as to control the first and second booster modules to transform the power voltage into driving voltage. The feedback module extracts a feedback current from a current flowing from the first to the second booster module and provides a feedback signal to the control module. When the feedback current exceeds a current threshold, the control module cuts off the PWM signal output so as to achieve short-circuit protection. A liquid crystal panel incorporating the above short-circuit protection circuit is also provided.

In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

An electrostatic discharge (ESD) protection device includes a substrate including a plurality of active fins and a plurality of grooves. The ESD protection device includes an insulation layer on the active fins and the grooves, and a gate electrode on the active fins. The ESD protection device includes a first impurity region adjacent to a first side of the gate electrode, and a second impurity region adjacent to a second side of the gate electrode. The second side of the gate electrode may be arranged opposite to the first side. The ESD protection device includes an electrode pattern of a capacitor overlapping the first impurity region, a resistor overlapping the second impurity region, and a connection structure electrically connecting the electrode pattern, the gate electrode, and the resistor to each other.

In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

An electrostatic discharge (ESD) device for an integrated circuit includes a substrate having a longitudinally extending fin dispose thereon. A first n-type FinFET (NFET) is disposed within the fin. The NFET includes an n-type source, an n-type drain and a p-well disposed within the substrate under the source and drain. A p-type FinFET (PFET) is disposed within the fin. The PFET includes a p-type source/drain region and an n-well disposed within the substrate under the source/drain region. The n-well and p-well are located proximate enough to each other to form an np junction therebetween. The p-type source/drain region of the PFET and the n-type drain of the NFET are electrically connected to a common input node.

A TFT display device and a method for producing the device are disclosed. The TFT display device includes: a first metal layer, on which a first silicon nitride film is deposited; a second metal layer deposited on the first silicon nitride film and etched to form a pattern, wherein a second silicon nitride film is deposited on the second metal film; and a via hole, wherein the first metal layer and/or the second metal layer are disconnected in the overlapping region. The first silicon nitride layer and the second silicon nitride layer are etched to form the via hole On the disconnected position, and an ITO conductive film is deposited to electrically connect the disconnected position. According to the present invention, by means of the above-mentioned way, the TFT display device will have less damage by ESD. The yield rate of the product is increased, and the product competitiveness is enhanced.

An analogue semiconductor device and a semiconductor IC device including the same include a substrate having a transistor, a MIM capacitor electrically separated from the transistor on the substrate and having a lower electrode, a dielectric layer and an upper electrode, interlayer insulation covering the transistor and the MIM capacitor and a BEOL resistor connected to the upper electrode and equipotential with the lower electrode. The BEOL resistor has a relatively large and easy-variable resistance with minimized parasitic capacitance between the resistor and the lower electrode of the MIM capacitor.

A semiconductor integrated circuit is provided, including: a first switch circuit; a logic circuit, coupled to the first switch circuit, a first floating diffusion point being defined between the first switch circuit and the logic circuit; a second switch circuit, coupled to the logic circuit, a second floating diffusion point being defined between the second switch circuit and the logic circuit; and a voltage holding circuit, coupled to the first floating diffusion point and the second floating diffusion point, and used to adjust the voltages of the floating diffusion points. The voltage holding circuit increases or decreases the voltage values of the first floating diffusion point and the second floating diffusion point. Thereby, the influence of long recovery time on the semiconductor integrated circuit is improved, and the stability is ensured.