A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

A display device includes a display panel having a display area and a non-display area, at least one thin-film transistor disposed in the non-display area, at least two or more divided capacitors disposed in the non-display area, and a bridge line for connecting two neighboring divided capacitors with each other among the at least two or more divided capacitors. The non-display area includes a light-blocking film disposed on a substrate and having a stepped first region and a flat second region, and a buffer and gate insulating film disposed on the light-blocking film, and having a bent first region disposed on the stepped first region of the light-blocking layer and a flat second region disposed on the flat second region of the light-blocking layer.

Systems, methods and apparatus are provided for transceiver capacitance reduction. An example apparatus can comprise a first signal driver of a transceiver, a second signal driver of the transceiver, and an input/output (I/O) pad coupled to the first and second signal drivers. The apparatus can further comprise a resistor divider of a plurality of resistor dividers coupled to the first signal driver. The resistor divider, when enabled, can reduce capacitance of the first signal driver and maintain the reduced capacitance while the second signal driver is actively driving a signal.

A display device includes: a substrate including a display area and a peripheral area positioned outside the display area; a first power supply line positioned in the peripheral area; a first insulating layer positioned on the first power supply line; and a second power supply line positioned on the first insulating layer in the peripheral area. The first power supply line includes a first main wire extending in a first direction and a first sub-wire diverging toward the display area from the first main wire, the second power supply line includes a second main wire extending in the first direction and a second sub-wire diverging toward the display area from the second main wire, the first main wire includes an internal edge positioned near the first sub-wire and an external edge facing the internal edge, and the second main wire does not overlap the internal edge in a plan view.

An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit.

A material removal process referred to as spalling is used to provide flexible and stretchable sensors that can be used for healthcare monitoring, bio-medical devices, wearable electronic devices, artificial skin, large area sensing, etc. The flexible and stretchable sensors of the present application have high sensitivity that is comparable to that of a bulk silicon sensor. The flexible and stretchable sensors comprise single crystalline spring-like structures that couple various resistor structures together.

A display panel includes a substrate, a first stacking unit, and a second stacking unit. The first stacking unit is disposed on the substrate and connected to a scan line. The first stacking unit includes a first conducting layer, a second conducting layer, at least one first through hole, and a first protruding portion. The first conducting layer is interposed between the second conducting layer and the substrate. The first through hole connects the first conducting layer and the second conducting layer. The position of the first protruding portion is relative to the position of the second protruding portion.

Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.

Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.

A display device comprising a display panel that includes an active area, the active area including a data line positioned on a substrate in a first direction and transferring a data signal, a gate line positioned on the substrate in a second direction and transferring a gate signal, a thin film transistor connected to the gate line and the data line, and a plurality of pixels driven by the thin film transistor, a first pad coupled to a first signal line disposed in a data signal area wherein the first signal line is connected to the data line, and a first non-signal line disposed in a first non-signal area wherein the first non-signal line is disconnected from the data line, the first non-signal area being disposed outside the data signal area, a second pad coupled to a second signal line disposed in a gate signal area wherein the second signal line is connected to the gate line, and a second non-signal line disposed in a second non-signal area wherein the second non-signal line is disconnected from the gate line, the second non-signal area being disposed outside the gate signal area; and a dummy pattern disposed between the data signal area and the first non-signal area, or disposed between the gate signal area and the second non-signal area.