A cascode transistor circuit having an active region, the active region having a source, a drain, a floating source/drain, a first gate disposed between the source and the floating source/drain and a second gate disposed between the floating source/drain and the drain. A first gate pad is displaced from the active region and is electrically connected to the first gate and a second gate pad is displaced from the active region and is electrically connected to the second gate. The first and the second gate pads are disposed on opposite sides of the active region.

The present disclosure provides a substrate and a display device. The substrate includes an internal region and a peripheral region surrounding the internal region, a plurality of signal wires and at least one ground wire being included in the peripheral region; any two adjacent signal wires, as well as the signal wire and the ground wire which are adjacent to each other, are connected through a selective connection structure; and the selective connection structure is capable of being connected in case of electro-static discharge. In the substrate and the display device provided by the present disclosure, because static electricity in each signal channel inside the substrate can be finally discharged via the ground wire in case of ESD, ESD protection for each signal channel in the internal region and the signal wire connected thereto can be achieved.

Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

A display panel and a display device are provided. The display panel includes an array substrate and an opposite substrate arranged oppositely; a sealant disposed in non-display areas; and a peripheral wiring disposed in the non-display areas of the array substrate and/or the opposite substrate and including at least one electrostatic discharge (ESD) structure.

The described techniques address issues associated with electrostatic discharge (ESD) protection for multi-die integrated circuits (ICs). The techniques include the use of two or more semiconductor dies within a multi-die IC, which may include a first semiconductor die without ESD protection but with full ESD exposure. The first semiconductor receives ESD protection via a second semiconductor die that is integrated as part of the same package with the first semiconductor die. The second semiconductor die may be electrically more remote from ESD-exposed pins compared to the first semiconductor die. The first semiconductor die may include integrated passive devices. The second semiconductor die enables ESD protection for both semiconductor dies in the same integrated IC package.

A silicon-controlled rectifier (SCR) includes a first-type field, a second-type first field and a second-type second field disconnectedly formed in a first-type well; an entire first-type doped region formed within the first-type field; a segmented second-type doped region formed within the second-type first field; and a segmented first-type doped region formed within the second-type second field.

An electrostatic discharge protection element is provided, which leads out the electrostatic discharge current between an internal circuit and an input/output terminal in the event of electrostatic discharge. The electrostatic discharge protection element includes an I/O pad, conductor, and a gap structure. The I/O pad is connected between the I/O terminal and the internal circuit, and the conductor is connected to a ground terminal. The gap structure is disposed between the I/O pad and the conductor, which is configured to establish a path from the I/O pad to the conductor connected to the ground terminal for conducting the electrostatic discharge current.

A device comprises a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of a first dopant type. A contact structure is in direct contact with the first and second implant regions and the electrode. A third implant region has a second dopant type different from the first dopant type. A bulk contact is provided on the third implant.

The present invention relates to a display panel including a static electricity preventing pattern and a display device having the same. An aspect of the present invention provides a display device or a display panel in which a dummy pattern having a pattern identical to or similar to a line of a signal area is positioned between the signal area and a non-signal area, in a pad including the signal area and the non-signal area.

A display apparatus includes a timing controller configured to output a gate control signal through gate control lines, a gate driver configured to output gate signals in response to the gate control signal provided from the gate control lines, pixels configured to receive data voltages in response to the gate signals, and first and second static electricity prevention parts connected to the gate control lines in parallel configured to discharge a static electricity. Each of the first and second static electricity prevention parts is configured to form current paths, which are smaller in number than a number of the gate control lines, to discharge the static electricity and the static electricity configured to be discharged by the first static electricity prevention part has a polarity different from a polarity of the static electricity configured to be discharged by the second static electricity prevention part.