A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700.

A manufacturing method of this invention includes: a step of slicing a silicon single crystal containing boron as an acceptor and obtaining a non-heat-treated silicon wafer, a step of determining a boron concentration with respect to the non-heat-treated silicon wafer, and a step of determining an oxygen donor concentration with respect to the non-heat-treated silicon wafer, in which a determination as to whether or not to perform a heat treatment at a temperature of 300 C. or more on the non-heat-treated silicon wafer is made based on a boron concentration determined in the step of determining a boron concentration, and an oxygen donor concentration determined in the step of determining an oxygen donor concentration. By this means, a wafer in which unevenly distributed LPDs that are present on the wafer are reduced is obtained.

A semiconductor process including the following step is provided. A sacrificial layer is formed in a substrate. The sacrificial layer and the substrate are etched to form a trench in the sacrificial layer and the substrate. A first isolation material fills the trench, thereby a first isolation structure being formed. The sacrificial layer is patterned to form a plurality of sacrificial patterns. A plurality of spacers are formed beside the sacrificial patterns respectively. The sacrificial patterns are removed. Layouts of the spacers are transferred into the substrate, so that a plurality of fin structures are formed in the substrate. The spacers are then removed. The present invention also provides a semiconductor structure formed by said semiconductor process.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.

The invention relates to a method for forming a device (5) comprising graphene, the method comprising the following steps: a step S1 of forming a graphene film (1) on a substrate (2); a step S2 of depositing, on the graphene film (1), a functionalisation material (3) configured to modify physicochemical properties of the graphene film (1), the deposition of functionalisation material being configured to partially cover the graphene film (1); a step S3 of gas-phase deposition of a polymer material (4) covering the graphene film (1) and the functionalisation material (3); anda step S4 of removing the substrate (2) so that the polymer material (4) forms a support for the graphene film (1).

The invention relates to a method for forming a device (5) comprising graphene, the method comprising the following steps: a step S1 of forming a graphene film (1) on a substrate (2); a step S2 of depositing, on the graphene film (1), a functionalisation material (3) configured to modify physicochemical properties of the graphene film (1), the deposition of functionalisation material being configured to partially cover the graphene film (1); a step S3 of gas-phase deposition of a polymer material (4) covering the graphene film (1) and the functionalisation material (3); anda step S4 of removing the substrate (2) so that the polymer material (4) forms a support for the graphene film (1).

A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor.

The crystal plane in the interior of the diamond substrate has a curvature higher than 0 km.sup.1 and equal to or lower than 1500 km.sup.1 by preparing a base substrate, forming a plurality of pillar-shaped diamonds formed of diamond single crystals on one side of the base substrate, causing diamond single crystals to grow from tips of each pillar-shaped diamond, coalescing each of the diamond single crystals grown from the tips of each pillar-shaped diamond to form a diamond substrate layer, separating the diamond substrate layer from the base substrate, and manufacturing the diamond substrate from the diamond substrate layer.

The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 310.sup.8 pieces/cm.sup.2 or more and 110.sup.11 pieces/cm.sup.2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.

A SiC epitaxial wafer according to the present embodiment includes: a SiC substrate; and a SiC epitaxial layer deposited on the SiC substrate, wherein, in the SiC substrate, a density of basal plane dislocations is 1/cm.sup.2 or more and 3000/cm.sup.2 or less, and wherein, in the SiC epitaxial layer, a density of double Shockley (2SSF) type stacking faults is 4/cm.sup.2 or more and 10/cm.sup.2 or less, and a density of stacking faults other than the double Shockley (2SSF) type stacking faults is 2/cm.sup.2 or less.