A device including: a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions;
wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

The invention relates to a method for forming flip chip bumps using electroplating. The method allows the formation of flip chip bumps in a way that is compatible with already-formed sensitive electronic components, such as Josephson junctions, which may be used in quantum processing units. The invention also relates to a product and a flip chip package in which flip chip bumps are formed with the disclosed method.

A second-generation high temperature superconducting (HTS) strip and a preparation method thereof are provided. The second-generation HTS strip includes a superconducting strip body and a stabilizing layer arranged thereon. The stabilizing layer is a copper-graphene composite film with a total thickness of 2-30 microns on one side. The superconducting strip may be obtained by the preparation method of: (1) putting a superconducting strip body into a magnetron sputtering reaction chamber, followed by pumping to a high-level vacuum and filling with a working gas; (2) using copper and graphene as targets, and performing a sputter coating by controlling a magnetron sputtering power, to deposit the targets onto at least one surface of the superconducting strip body. The prepared HTS strips containing copper-graphene stabilizing layer with high strength and high conductivity may have 30%-70% higher tensile strength than conventional copper plated superconducting strips, with less than 10% IACS attenuation in conductivity.

A method for the production of a superconducting wire (20) uses a monofilament (1) having a powder core (3) that contains at least Sn and Cu, an inner tube (2), made of Nb or an alloy containing Nb, that encloses the powder core (3), and an outer tube (4) in which the inner tube (2) is arranged. The outer side of the inner tube (2) is in contact with the inner side of the outer tube (4) and the outer tube (4) is produced from Nb or from an alloy containing Nb. The outer tube is disposed in a cladding tube. The superconducting current carrying capacity of the superconducting wire is thereby improved.

Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include: a package substrate; a first die coupled to the package substrate; and a second die coupled to the second surface of the package substrate and coupled to the first die; wherein the first die or the second die includes quantum processing circuitry.

A REBCO superconductor tape that can achieve a lift factor greater than or equal to approximately 3.0 or 4.0 in an approximately 3 T magnetic field applied perpendicular to a REBCO tape at approximately 30 K. In an embodiment, the REBCO superconductor tape can include a critical current density less than or equal to approximately 4.2 MA/cm.sup.2 at 77 K in the absence of an external magnetic field. In another embodiment, the REBCO superconductor tape can include a critical current density greater than or equal to approximately 12 MA/cm.sup.2 at approximately 30 K in a magnetic field of approximately 3 T having an orientation parallel to a c-axis.

The present disclosure discloses a device and a method for fabricating a superconducting circuit including a superconducting qubit. The superconducting circuit comprises a bottom electrode interconnecting a superconducting qubit and a first part of the superconducting circuit. The bottom electrode comprises a bottom electrode of the superconducting qubit and a bottom electrode of the first part of the superconducting circuit. The bottom electrode of the superconducting qubit and the bottom electrode of the first part of the superconducting circuit are formed in a first superconducting layer.

Systems and techniques providing suitable chip structures for facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter can comprise a voltage-controlled oscillator and an antenna. The voltage-controlled oscillator can receive power-on signals from a microcontroller, thereby causing the voltage-controlled oscillator to generate an electromagnetic wave. The antenna can then direct the electromagnetic wave onto a set of one or more capacitor pads of a Josephson junction on a superconducting qubit chip, thereby annealing the Josephson junction. In another example, a voltage regulator and a digital-to-analog converter or digital-to-digital converter can be coupled in series between the microcontroller and the voltage-controlled oscillator, thereby allowing the voltage-controlled oscillator to be voltage and/or frequency tunable and eliminating the need for external power routing as compared to photonic laser annealing. In yet another example, a bipolar-junction and complementary metal-oxide semiconductor stack construction can be employed.

In the production of an internal-tin-processed Nb.sub.3Sn superconducting wire, the present invention provides a Nb.sub.3Sn superconducting wire that is abundant in functionality, such as, the promotion of formation of a Nb.sub.3Sn layer, the mechanical strength of the superconducting filament (and an increase in interface resistance), the higher critical temperature (magnetic field), and the grain size reduction, and a method for producing it. A method for producing a Nb.sub.3Sn superconducting wire according to an embodiment of the present invention includes a step of providing a bar 10 that has a Sn insertion hole 12 provided in a central portion of the bar 10 and a plurality of Nb insertion holes 14 provided discretely along an outer peripheral surface of the Sn insertion hole 12, and that has an alloy composition being Cu-xZn-yM (x: 0.1 to 40 mass %, M=Ge, Ga, Mg, or Al, provided that, for Mg, x: 0 to 40 mass %), a step of mounting an alloy bar with an alloy composition of Sn-zQ (Q=Ti, Zr, or Hf) into the Sn insertion hole 12 and inserting Nb cores into the Nb insertion holes 14, a step of subjecting the bar 10 to diameter reduction processing to fabricate a Cu-xZn-yM/Nb/Sn-zQ composite multicore wire with a prescribed outer diameter, and a step of subjecting the composite multicore wire to Nb.sub.3Sn phase generation heat treatment.

A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate, forming a first resist layer on the dielectric substrate, forming a second resist layer on the first resist layer, and forming a third resist layer on the second resist layer. The first resist layer includes a first opening extending through a thickness of the first resist layer, the second resist layer includes a second opening aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening aligned over the second opening and extending through a thickness of the third resist layer.