A heterojunction battery and a preparation method therefor are provided. The heterojunction battery includes a crystalline silicon layer, a first intrinsic amorphous silicon layer, an N-type doped microcrystalline silicon layer, a first transparent conductive layer, and a first metal electrode are sequentially arranged on a front surface of the crystalline silicon layer from inside to outside, and a second intrinsic amorphous silicon layer, a P-type doped microcrystalline silicon layer, a second transparent conductive layer, and a second metal electrode are sequentially arranged on a back surface of the crystalline silicon layer from inside to outside. A local reduction layer is formed on a surface of the first transparent conductive layer that is under the first metal electrode and/or on a surface of the second transparent conductive layer that is under the second metal electrode.

Provided are a heterojunction solar cell film deposition apparatus, method and system, a solar cell, a module, and a power generation system. The heterojunction solar cell film deposition apparatus is configured for amorphous silicon-based film deposition, and comprises a loading cavity, a preheating cavity, intrinsic process cavities, doping process cavities and an unloading cavity that are linearly arranged in sequence, the cavities being isolated from each other by means of an isolating valve. At least two intrinsic process cavities are provided and are configured for deposition by means of an intrinsic layer silicon film process; and at least one doping process cavity is provided and is configured for deposition by means of an N-type silicon film or P-type silicon film process. The preheating cavity comprises a heating preheating chamber and a preheating buffer chamber that is configured for adjusting the gas and pressure atmosphere.

A solar cell and a preparation method thereof are provided. A method for preparing the solar cell includes following steps: forming an amorphous silicon layer on a tunneling oxide layer at a first side; forming a doped polycrystalline silicon layer in a first process by a diffusion doping treatment; forming a doped oxide layer on the doped polycrystalline silicon layer in a second process; and after the doped oxide layer is formed, doping the first side selectively and heavily by a laser doping process, and forming a selective emitter region in a heavily doped region.

Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.

Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.

Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

A laser processing system can be utilized to produce high-performance interdigitated back contact (IBC) solar cells. The laser processing system can be utilized to ablate, transfer material, and/or laser-dope or laser fire contacts. Laser ablation can be utilized to remove and pattern openings in a passivated or emitter layer. Laser transferring may then be utilized to transfer dopant and/or contact materials to the patterned openings, thereby forming an interdigitated finger pattern. The laser processing system may also be utilized to plate a conductive material on top of the transferred dopant or contact materials.

Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality of symmetry-breaking surface corrugations, and removing the mask. The mask includes a pattern defined by mask material portions that cover first surface portions of the substrate and a plurality of mask space portions that expose second surface portions of the substrate, wherein the plurality of mask space portions are arranged in a lattice arrangement having a row and column, and the row is not oriented parallel to a [110] direction of the substrate. The patterning the substrate includes anisotropically removing portions of the substrate exposed by the plurality of spaces.

A tool useful in the manufacture of a semiconductor is disclosed. A mold is providing having an interior defining a planar capillary space. A coating substantially covers at least the planar capillary space of the graphite member. The coating is substantially non-reactive to silicon at temperatures greater than approximately 1420 degrees Centigrade.