An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

A method to form self-aligned middle-of-line (MOL) contacts between functional gate structures without the need of lithographic patterning and etching by using raised metal semiconductor alloy regions is provided. Raised metal semiconductor alloy regions are formed by reacting a metal layer with a semiconductor material in raised semiconductor material regions formed on portions of at least one active region of a substrate located between functional gate structures. The metal layer includes a metal capable of forming a metal semiconductor alloy with a large volume expansion such that the resulting metal semiconductor alloy regions can be raised to a same height as that of the functional gate structures. As a result, no lithographic patterning and etching between functional gate structures are needed when forming MOL contacts to these raised metal semiconductor alloy regions.

A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer; removing the dummy gate to form a first trench; forming first sub-fins in the semiconductor substrate under the hard mask layer in the first trench; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench; forming second sub-fins in the semiconductor substrate under the hard mask layer in the second trench; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench; forming third sub-fins in the semiconductor substrate under the hard mask layer in the third trench; and forming a third metal gate structure in the third trench.

A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

An epitaxial structure of semiconductor device includes a substrate, a recess, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The recess is formed in the substrate and disposed near a surface of the substrate, wherein the recess has a recess depth. The first epitaxial layer is disposed on surfaces of a sidewall and a bottom of the recess. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein the Ge concentration of the second epitaxial layer is greater than the Ge concentration of the first epitaxial layer. The third epitaxial layer is disposed on the surface of the second epitaxial layer, wherein the Ge concentration of the third epitaxial layer is greater than the Ge concentration of the second epitaxial layer, and the depth of the third epitaxial layer is about to about of the recess depth.

The present disclosure relates to a transistor device having a strained source/drain region. In some embodiments, the transistor device has a gate structure arranged over a semiconductor substrate. The transistor device also has a strained source/drain region arranged within the semiconductor substrate along a side of the gate structure. The strained source/drain region includes a first layer and a second layer over the first layer. The first layer has a strain inducing component with a first concentration profile that decreases as a distance from the second layer decreases, and the second layer has the strain inducing component with a second non-zero concentration profile that is discontinuous with the first concentration profile.

Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion.

A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 510.sup.21 to about 510.sup.22 atoms/cm.sup.2.

Disclosed are methods for stress memorization techniques and transistor devices prepared by such methods. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate having a channel region underlying, at least partially, the gate structure, the fabricating involving: performing a nitrogen ion implantation process by implanting nitrogen ions into the substrate to thereby form a stress region in the substrate, the stress region separated by the channel region, wherein the stress region has a stress region depth; forming a capping material layer above the NMOS transistor device; and, with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the stress region. In another embodiment, an amorphization ion implantation is performed prior to, after or along with the nitrogen ion implantation.