After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors.

A method for selectively removing silicon nitride is described. In particular, the method includes providing a substrate having a surface with silicon nitride exposed on at least one portion of the surface and SiGe.sub.x (x is greater than or equal to zero) exposed on at least another portion of the surface, and dispensing an oxidizing agent onto the surface of the substrate to oxidize the exposed SiGe.sub.x. Thereafter, the method includes dispensing a silicon nitride etching agent as a liquid stream onto the surface of the substrate to remove at least a portion of the silicon nitride.

The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate. A source/drain region having a strain inducing material is disposed along a side of the gate structure within a source/drain recess in the semiconductor substrate. The strain inducing material has a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess. The discontinuous germanium concentration profile provides improved strain boosting and dislocation propagation.

An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.

One illustrative example of a transistor device disclosed herein includes, among other things, a gate structure, first and second spacers positioned adjacent opposite sides of the gate structure, and a multi-layer gate cap structure positioned above the gate structure and the upper surface of the spacers. The multi-layer gate cap structure includes a first gate cap material layer positioned on an upper surface of the gate structure and on the upper surfaces of the first and second spacers, a first high-k protection layer positioned on an upper surface of the first gate cap material layer and a second gate cap material layer positioned on an upper surface of the high-k protection layer. The first and second gate cap layers comprise different materials than the first high-k protection layer.

Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of mono crystalline silicon on the surface of a semi conductive substrate, and forming a thin film of insulative material over the epitaxial layer. A second epitaxial layer is selectively, grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface.

A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.

A transistor device is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at a position where a gate is to be located. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are then converted into a transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are converted into a transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.