A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.

A semiconductor device includes: a substrate including a first wide-bandgap semiconductor material; a first region of a first conductivity type and a second region of a second conductivity type arranged above the substrate, where the first region and the second region include a second wide-bandgap semiconductor material, and where the first region and the second region form a Zener PN diode configured as an anti-fuse.

A lateral semiconductor device includes: a semiconductor substrate; a first insulator layer formed on the semiconductor substrate; and a semiconductor layer formed on the first insulator layer opposite to the semiconductor substrate. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, and an intermediate region interposed between the first region and the second region and defining a first lateral distance between the first region and the second region. The intermediate region has a lower doping concentration than the first region and the second region. A doping concentration of the first region at an interface to the intermediate region and a doping concentration of the second region at an interface to the intermediate region both exceed 110.sup.18 cm.sup.3. The first lateral distance is at most 800 nm.

A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.

The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.

An electronic device can include a substrate, lower and upper semiconductor layers over the substrate, and a doped region at the interface between the lower and upper semiconductor layers. The doped region can have a conductivity type opposite that of a dopant within the lower semiconductor layer. Within the lower semiconductor layer, the dopant can have a dopant concentration profile that has a relatively steeper portion adjacent to the substrate, another relatively steeper portion adjacent to an interface between the first and second semiconductor layers, and a relatively flatter portion between the relative steeper portions. A diode lies at a pn junction where a second dopant concentration profile of the first doped region intersects the relatively flatter portion of the first dopant concentration profile. The electronic device can be formed using different processes described herein.

In accordance with an embodiment, semiconductor component includes a compound semiconductor material based semiconductor device coupled to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.

A semiconductor device includes a Zener diode having an anode layer and a cathode layer. The Zener diode provides an electrostatic discharge (ESD) path for ESD signals. At least two channel diodes are coupled to the ESD path of the Zener diode. Each of the channel diodes includes a common cathode layer and a separate anode region. The common cathode layer of the channel diodes is disposed on the cathode layer of the Zener diode. At least two channels are provided where each channel is coupled to one of the separate anode regions to provide an electrical connection for protected signal paths to the ESD path.

A compact LED module and a method of manufacturing such an LED module are provided. The LED module includes a first-pole first lead, a first-pole second lead, a first-pole third lead, a second-pole first lead, a second-pole second lead, a second-pole third lead, a first LED chip, a second LED chip, a third LED chip, and a housing. A distal end of the first-pole first lead is offset toward a second-pole side in a first direction with respect to both a distal end of the second-pole second lead and a distal end of the second-pole third lead.