A light emitting diode package for a directional display may comprise light emitting diodes and a protection diode. The protection diode may be arranged in a well that is at a different location to the well that the light emitting diodes are arranged. The directional display may include a waveguide. The waveguide may include light extraction features arranged to direct light from an array of light sources by total internal reflection to an array of viewing windows and a reflector arranged to direct light from the waveguide by transmission through extraction features of the waveguide to the same array of viewing windows. The brightness of the directional display can be increased. An efficient and bright directional display system can be achieved. Efficient light baffling for light escaping from the edge of the waveguide is achieved through light deflecting extraction films.

A diode includes a semiconductor body, a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, a base region arranged between the first and second emitter regions and having a lower doping concentration than the first and second emitter regions, a first emitter electrode electrically coupled to the first emitter region, a second emitter electrode in electrical contact with the second emitter region, a control electrode arrangement comprising a first control electrode section and a first dielectric layer arranged between the first control electrode section and the semiconductor body, and at least one pn junction extending to the first dielectric layer, or arranged distant to the first dielectric layer by less than 250 nm. The breakdown voltage of the diode is adjusted by applying a control potential to the first control electrode section.

A semiconductor device provides reduced size and increased performance, and includes a semiconductor layer having a surface layer including first and second semiconductor regions connected to first and second potentials, respectively; a third semiconductor region provided inside the first semiconductor region and connected to a third potential; a fourth semiconductor region provided inside the second semiconductor region and connected to the third potential; a plurality of a first element provided in each of the first, second, third, and fourth semiconductor regions; a first isolation region provided between and in contact with the first and second semiconductor regions, electrically connected to the semiconductor layer, and connected to a fourth potential; and a second isolation region which encloses the periphery of and maintains a withstand voltage of the first and second semiconductor regions. The third and fourth potentials are lower than the second potential, which is lower than the first potential.

A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.

An LED (Light Emitting Diode) module includes an LED unit having one or more LED chips and a case. The case includes: a body including a base plate made of ceramic, the base plate having a main surface and a bottom surface opposite to the main surface; a through conductor penetrating through the base plate; and one or more pads formed on the main surface and making conductive connection with the through conductor, the pads mounting thereon the LED unit. The through conductor includes a main surface exposed portion exposed to the main surface and overlapping the LED unit when viewed from top, a bottom surface reaching portion connected to the main surface exposed portion and reaching the bottom surface. The pads cover at least a portion of the main surface exposed portion.

A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.

A light emitting diode (LED) package includes an LED chip, a first lead frame and a second lead frame electrically connected to the LED chip and separated by a space, and a housing disposed on the first lead frame and the second lead frame. The housing includes an external housing surrounding a cavity, the cavity exposing a first portion of the first lead frame and a first portion of the second lead frame, and an internal housing disposed in the space, the internal housing covering a top portion of the first lead frame and a top portion of the second lead frame.

In one embodiment, electrostatic discharge (ESD) devices are disclosed.

The invention relates to a semiconductor isolation structure. More particularly, the present invention relates to a semiconductor isolation structure suitable for providing high voltage isolation. Embodiments disclosed include a semiconductor structure (10) comprising: a first semiconductor region (R1), a second semiconductor region (R2) within the first semiconductor region (R1), and a voltage isolator (11) separating the first and second semiconductor regions (R1, R2), the voltage isolator (11) comprising: a nested series of insulating regions (T1, T2) around the perimeter of the second semiconductor region (R2), an intermediate semiconductor region (I1, I2) between each adjacent pair of nested insulating regions (T1, T2), and a voltage control device (12) comprising a conducting element (D1-D3) connected to at least one intermediate semiconductor region (I1, I2) in parallel with the at least one insulating region (T1, T2), so as to control a voltage across the at least one insulating region (T1, T2).

One or more Zener diodes and a field effect transistor having a drain connected in series with the one or more Zener diodes are integrally formed by a plurality of doped regions in the same P-type semiconductor substrate and separated by a punch through stop region. An N-type region is formed under the one or more Zener diodes.