In accordance with various embodiments of the disclosed subject matter, a fin field effect transistor and a fabricating method thereof are provided. In some embodiments, the method comprises: providing a semiconductor substrate including a fin part protruded above a surface of the semiconductor substrate; forming a metal sulfide layer on the semiconductor substrate, and across the top and side walls of the fin part, wherein the metal sulfide layer is used as a channel region of the fin field effect transistor; forming a first gate electrode structure on the metal sulfide layer and across the top and side walls of the fin part; and forming a source electrode layer and a drain electrode layer on both sides of the first gate structure respectively.

A semiconductor device includes a first gate isolation structure. A second gate isolation structure is spaced apart from the first gate isolation structure in a first direction. A first active pattern is disposed between the first and second gate isolation structures. The first active pattern extends longitudinally in a second direction crossing the first direction. A second active pattern is disposed between the first and second gate isolation structures. The second active pattern extends longitudinally in the second direction and is spaced apart from the first active pattern in the first direction. Gate structures are disposed between the first and second gate isolation structures. The gate structures directly contact the first and second gate isolation structures. A length of the first gate isolation structure in the second direction is greater than a length of the second gate isolation structure in the second direction.

Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening.

An IC structure a first circuit and a second circuit. The first circuit includes a plurality of first fin structures, and one or more first gate structures extending across the plurality of first fin structures. The second circuit includes a plurality of second fin structures, and one or more second gate structures extending across the plurality of second fin structures. In a plan view, one of second fin structures has a width greater than a width of one of the first fin structures. A spacing between adjacent two of the plurality of second fin structures is less than a spacing between adjacent two of the plurality of first fin structures.

The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

A method for forming a semiconductor device includes forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the recess, wherein the first conductive line extends across the fin structure and wraps a first portion of the fin structure; forming a second conductive line in the same layer as the first conductive rail, wherein the second conductive line extends across the fin structure and contacts a second portion of the fin structure different from the first portion; and forming an isolation region on the substrate to separate the first conductive rail from the second conductive line.

Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si.sub.3N.sub.4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.

Methods and structures for inserting disposable interposers include forming a first gate over a first fin and a first spacer layer on sidewalls of the first gate, and a second gate over a second fin and a second spacer layer on sidewalls of the second gate. The method further includes replacing, within the first fin, epitaxial layers of a second composition with disposable interposers disposed beneath the first gate and first inner spacers on opposing ends of the disposable interposers. The method further includes etching back, within the second fin, opposing lateral ends of the epitaxial layers of the second composition to form recesses disposed beneath the second spacer layer and between adjacent epitaxial layers of the first composition. The method further includes forming second inner spacers, within the second fin, within each of the recesses on the opposing lateral ends of the epitaxial layers of the second composition.