Patent classifications
H10F77/244
BANDGAP GRADING OF CZTS SOLAR CELL
A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including CuZnSnS(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.
HIGH-EFFICIENCY SOLAR CELL STRUCTURES AND METHODS OF MANUFACTURE
Solar cells of varying composition are disclosed, generally including a central substrate, conductive layer(s), antireflection layers(s), passivation layer(s) and/or electrode(s). Multifunctional layers provide combined functions of passivation, transparency, sufficient conductivity for vertical carrier flow, the junction, and/or varying degrees of anti-reflectivity. Improved manufacturing methods including single-side CVD deposition processes and thermal treatment for layer formation and/or conversion are also disclosed.
Bandgap grading of CZTS solar cell
A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including CuZnSnS(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.
SOLAR CELL WITH GRAPHENE-SILICON QUANTUM DOT HYBRID STRUCTURE AND METHOD OF MANUFACTURING THE SAME
Disclosed are a solar cell and a method of manufacturing the same. The solar cell with a graphene-silicon quantum dot hybrid structure according to an embodiment of the present disclosure includes a hybrid structure including a silicon quantum dot layer, in which a silicon oxide layer includes a plurality of silicon quantum dots; a doped graphene layer formed on the silicon quantum dot layer, and an encapsulation layer formed on the doped graphene layer; and electrodes formed on upper and lower parts of the hybrid structure.
Silicon heterojunction photovoltaic device with wide band gap emitter
A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
Method for producing a photovoltaic solar cell having at least one heterojunction passivated by means of hydrogen diffusion
The invention relates to a method for producing a photovoltaic solar cell having at least one hetero-junction, including the following steps: A) providing a semiconductor substrate having base doping; B) producing a hetero-junction on at least one side of the semiconductor substrate, which hetero-junction has a doped hetero-junction layer and a dielectric tunnel layer arranged indirectly or directly between the hetero-junction layer and the semiconductor substrate; C) heating at least the hetero-junction layer in order to improve the electrical quality of the heterojunction. The invention is characterized in that, in a step D after step C, hydrogen is diffused into the hetero-junction layer and/or to the interface between the tunnel layer and the semiconductor substrate.
Electroconductive nanowire network, and electroconductive substrate and transparent electrode using same, and method for manufacturing electroconductive nanowire network, electroconductive substrate, and transparent electrode
There are provided a conductive nanowire network, a conductive board and transparent electrode utilizing it, and a method for producing the same. The conductive nanowire network of the invention has essentially unbroken, continuous conductive nanowires randomly formed into a network. In the method for producing a conductive nanowire network according to the invention, nanofibers are applied in a random network-like fashion onto a substrate covered with a conductive layer, the conductive layer regions that are not covered with the nanofibers are removed, and then the nanofibers are removed. The network structure (wire diameter and network density) are also controlled to obtain a transparent electrode exhibiting both transparency and conductivity.
SENSOR COMPRISING A PHOTOVOLTAIC DEVICE
In one example, a sensor comprises a photovoltaic device. The photovoltaic device comprises a core having a shape that is at least partially spherical, an absorber disposed over the core, and a transparent conductor disposed over the absorber. Other examples and related methods are also disclosed herein.
SOLAR CELL
A solar cell is disclosed, which includes a crystalline semiconductor substrate of a first conductive type, a front doped layer on a front surface of the semiconductor substrate and forming a hetero junction with the semiconductor substrate, a back doped layer on a back surface of the semiconductor substrate and forming a hetero junction with the semiconductor substrate, a front transparent conductive layer on the front doped layer, a back transparent conductive layer under the back doped layer. One of the front doped layer and the back doped layer has a second conductive type opposite to the first conductive type to form a p-n junction with the semiconductor substrate, and the other of the front doped layer and the back doped layer has the first conductive type. A planar area of the front transparent conductive layer is larger than a planar area of the back transparent conductive layer.
SOLAR CELL
A solar cell is disclosed. The solar cell includes a crystalline semiconductor substrate containing impurities of a first conductivity type, a front doped layer located on a front surface of the semiconductor substrate, a back doped layer located on a back surface of the semiconductor substrate, a front transparent conductive layer located on the front doped layer and having a first thickness, a front collector electrode located on the front transparent conductive layer, a back transparent conductive layer located under the back doped layer and having a second thickness, and a back collector electrode located under the back transparent conductive layer. The first thickness of the front transparent conductive layer and the second thickness of the back transparent conductive layer are different from each other, and a sheet resistance of the front transparent conductive layer is less than a sheet resistance of the back transparent conductive layer.