An apparatus includes a first wall and a second wall extending from a planar surface of a substrate to a wall height, and a plurality of electrodes disposed on the first wall and the second wall. The first wall and the second wall can be spaced apart from one another along a first axis on the planar surface. The plurality of electrodes can be configured to generate an electric field to trap an ion at a trapping position located between the first wall and the second wall. A vertical distance between the trapping position and the planar surface of the substrate can be smaller than the wall height.

Main cells that constitute a semiconductor element having a trench gate structure include first cells, and second cells having a structure in which gate insulating films are more easily broken by energization than those in the first cells, and the number of which is smaller than that of the first cells. At a time of driving the semiconductor element, a common gate drive voltage is applied to gate electrodes of the first cells and the second cells. An electrical characteristic is measured to detect failure of the second cells due to energization at the time of driving. The gate electrodes of the failed second cells are electrically isolated from the gate electrodes of the first cells so that the gate drive voltage is not applied to the failed second cells. The failure of the first cells is predicted based on the failure of the second cells.

Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.

Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.

A quantum information processing device including a semiconductor substrate. An optical resonator is coupled to the substrate. The optical resonator supports a first photonic mode with a first resonator frequency. The quantum information processing device includes a non-gaseous chalcogen donor atom disposed within the semiconductor substrate and optically coupled to the optical resonator. The donor atom has a transition frequency in resonance with the resonator frequency. Also disclosed herein are systems, devices, articles and methods with practical application in quantum information processing including or associated with one or more deep impurities in a silicon substrate optically coupled to an optical structure.

A semiconductor device according to an embodiment includes a transistor region and a diode region. The transistor region includes a first silicon carbide region of n-type having a first portion in contact with a first plane, a second silicon carbide region of p-type, a third silicon carbide region of n-type, and a gate electrode. The diode region includes the first silicon carbide region of n-type having a second portion in contact with the first plane and a fourth silicon carbide region of p-type. The semiconductor device includes a gate wiring electrically connected to the gate electrode. A distance between a high-concentration portion included in the fourth silicon carbide region and the gate wiring is larger than a distance between a high-concentration portion included in the second silicon carbide region and the gate wiring.

There is provided a logic gate comprising a semiconductor device. The semiconductor device includes a charge reservoir layer disposed between a first charge accepting layer and a second charge accepting layer. The first charge accepting layer defines a first current flow path that is connected to a common output contact at one end and a drive contact at the other end. The second charge accepting layer defines a current flow path that is connected to the common output contact at one end and a ground contact at the other end. The charge reservoir layer comprises a potential well having a lowest energy state for mobile charge carriers that is at a lower energy than the lowest energy state for mobile charge carriers of both the first and second charge accepting layers. The logic gate further comprises a control gate and a ground electrode that are separated from the charge accepting layers by non-conducting layers. The control gate and the ground electrode are configured to apply an input voltage across the semiconductor device, such that mobile charge carriers confined within the charge reservoir layer are transferred to the first charge accepting layer at a first applied input voltage and transferred to the second charge accepting layer at a second applied input voltage.

There is provided a logic gate comprising a semiconductor device. The semiconductor device includes a charge reservoir layer disposed between a first charge accepting layer and a second charge accepting layer. The first charge accepting layer defines a first current flow path that is connected to a common output contact at one end and a drive contact at the other end. The second charge accepting layer defines a current flow path that is connected to the common output contact at one end and a ground contact at the other end. The charge reservoir layer comprises a potential well having a lowest energy state for mobile charge carriers that is at a lower energy than the lowest energy state for mobile charge carriers of both the first and second charge accepting layers. The logic gate further comprises a control gate and a ground electrode that are separated from the charge accepting layers by non-conducting layers. The control gate and the ground electrode are configured to apply an input voltage across the semiconductor device, such that mobile charge carriers confined within the charge reservoir layer are transferred to the first charge accepting layer at a first applied input voltage and transferred to the second charge accepting layer at a second applied input voltage.

A semiconductor device includes first and second transistors on a substrate of first conductivity type, and a well region between at least one of the first and second transistors and the substrate, and has second conductivity type different from first conductivity type. The first transistor includes a first channel layer on the substrate, a first barrier layer on the first channel layer, a first gate electrode on the first barrier layer, and a first source electrode and a first drain electrode on opposite sides of the first gate electrode, and connected to the first channel layer. The second transistor includes a second channel layer on the substrate, a second barrier layer on the second channel layer, a second gate electrode on the second barrier layer, and a second source electrode and a second drain electrode on opposite sides of the second gate electrode, and connected to the second channel layer.

The semiconductor device includes a semiconductor layer having an active portion and a gate finger portion, an MIS transistor formed at the active portion including a gate trench and a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.