The semiconductor device includes a semiconductor layer having an active portion and a gate finger portion, an MIS transistor formed at the active portion including a gate trench and a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.

Disclosed are an MPS diode device and a preparation method therefor. The MPS diode device comprises a plurality of cells arranged in parallel, wherein each cell comprises a cathode electrode, and a substrate, epitaxial layer, buffer layer, and anode electrode that are formed in succession on the cathode electrode; two active regions are formed on the side of the epitaxial layer away from the substrate; the width of forbidden band of the buffer layer is greater than the width of forbidden band of the epitaxial layer, and a material of the buffer layer and a material of the epitaxial layer are allotropes; and first openings are formed at the positions in the buffer layer opposite to the active regions, and an ohmic metal layer is formed in the first openings.

A quantum information processing device including a semiconductor substrate. An optical resonator is coupled to the substrate. The optical resonator supports a first photonic mode with a first resonator frequency. The quantum information processing device includes a non-gaseous chalcogen donor atom disposed within the semiconductor substrate and optically coupled to the optical resonator. The donor atom has a transition frequency in resonance with the resonator frequency. Also disclosed herein are systems, devices, articles and methods with practical application in quantum information processing including or associated with one or more deep impurities in a silicon substrate optically coupled to an optical structure.

A transistor with improved low-frequency noise characteristics is disclosed. Phase complexing channel layer having quantum dots distributed within an amorphous matrix is formed, and a surface stabilization layer is formed in contact with the phase complexing channel layer. The surface stabilization layer has a repeating structure of an inorganic insulating layer and an organic shielding layer. Since the quantum dots of the phase complexing channel layer are in a quantized state, carriers trapped in the quantum dots are limited. Even if current is generated at the phase complexing channel layer by the drain-source voltage, the carriers trapped at the quantum dots are maintained at a constant level. Accordingly, the drain-source current is constant even when the gate voltage increases, and the noise component of the gate voltage is not reflected in the drain current.

Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.

Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.