A reverse blocking semiconductor device is manufactured by introducing impurities of a first conductivity type into a semiconductor substrate of the first conductivity type through a process surface to obtain a process layer extending into the semiconductor substrate up to a first depth, and introducing impurities of a second, complementary conductivity type into the semiconductor substrate through openings of an impurity mask provided on the process surface to obtain emitter zones of the second conductivity type extending up to a second depth deeper than the first depth and channels of the first conductivity type between the emitter zones. Exposed portions of the process layer are removed above the emitter zones.

A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-connected distributed diode, where the base region is connected neither to the collector electrode nor to the emitter electrode. The bipolar transistor has unusually high emitter-to-base and emitter-to-collector reverse breakdown voltages. In the case of a PNP-type RBJT, an N base region extends into a P epitaxial layer, and a plurality of P++ collector regions extend into the base region. Each collector region is annular, and rings a corresponding diode cathode region. Parts of the epitaxial layer serve as the emitter, and other parts serve as the diode anode. Insulation features separate metal of the collector electrode from the base region, and from P type silicon of the epitaxial layer, so that the diode cathode is separated from the base region. This separation prevents base current leakage and reduces power dissipation during steady state on operation.

A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty.

A semiconductor device capable of carrying out temperature detection appropriately by a temperature sensor is provided. In a semiconductor device disclosed herein, a first width of a first portion within a front surface insulating film (that is, part located in an upper part of an active region among a part extending along a first side of a front surface electrode that is closer to the temperature sensor) is wider than a second width of a second portion within the front surface insulating film (that is, part located in the upper part of the active region among a part extending along a second side of the front surface electrode).

A power semiconductor device includes: a semiconductor body having a first surface and a mesa portion that includes a surface part of the first surface and a body region; at least two trenches extending from the first surface into the semiconductor body along a vertical direction, each trench including a trench electrode and trench insulator insulating the trench electrode from the semiconductor body, the mesa portion being laterally confined by the trenches in a first vertical cross-section along a first lateral direction; and a contact plug in contact with the body region. The contact plug and trench electrode of a first trench laterally overlap at least partially in the first vertical cross-section. A protection structure having a portion arranged within the first trench is arranged between the contact plug and trench electrode of the first trench. The protection structure may be an electrically insulation structure or a protective device structure.

In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.

A transistor includes first and second load terminals and a semiconductor body coupled to both terminals. The semiconductor body includes: a drift region having dopants of a first conductivity type; a transistor section for conducting a forward load current and having a control head coupling the first load terminal to a first side of the drift region; and a diode section for conducting a reverse load current. A diode port couples the second load terminal to a second side of the drift region and includes: a first emitter electrically connected to the second load terminal and having dopants of the first conductivity type for injecting majority charge carriers into the drift region; and a second emitter having dopants of a second conductivity type for injecting minority charge carriers into the drift region. A pn-junction transition between the first and second emitters has a breakdown voltage of less than 10 V.

A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; an insulating portion provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region and having a hicher carrier concentration of the second conductivity type than that of the second semiconductor region; and a first electrode provided on the insulating portion and the third semiconductor region, the first electrode having a portion which is aligned with the second semiconductor region in a second direction perpendicular to a first direction being from the first semiconductor region to the second semiconductor region, and the first electrode being in contact with the second semiconductor region and the third semiconductor region.

An influence of a gate interference is suppressed and a reverse recovery property of a diode is improved. A diode includes a diode region located between the first boundary trench and the second boundary trench and a first and second IGBT regions. An emitter region and a body region are provided in each of the first and second IGBT regions. Each body region includes a body contact portion. An anode region is provided in the diode region. The anode region includes an anode contact portion. An interval between the first and second boundary trenches is equal to or longer than 200 m. An area ratio of the anode contact portion in the diode region is lower than each of an area ratio of the body contact portion in the first IGBT region and an area ratio of the body contact portion in the second IGBT region.

An IGBT includes an emitter electrode, base regions, an emitter region, a collector region, a collector electrode, a gate insulating film provided in contact with the silicon carbide semiconductor region, the emitter region, and the base region, and a gate electrode that faces the gate insulating film. A FWD includes a base contact region provided adjacent to the emitter region and electrically connected to the emitter electrode, and a cathode region disposed in the upper layer part on the other main surface side of the silicon carbide semiconductor region, provided adjacent to the collector region, and electrically connected to the collector electrode. The IGBT further includes a reduced carrier-trap region disposed in a principal current-carrying region of the silicon carbide semiconductor region located above the collector region and having a smaller number of carrier traps than the silicon carbide semiconductor region located above the cathode region.