An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

A semiconductor device includes: a plurality of transistors on a substrate, each transistor of the plurality of transistors including a source region, a drain region, a gate structure, a polarization modulation portion, and a polarization layer. The polarization modulation portion of each of the plurality of transistors is on the polarization layer, the plurality of transistors includes a first transistor having a first threshold voltage that has a first fixed value, and the plurality of transistors includes a second transistor having a second threshold voltage that has a second fixed value different from the first fixed value.

A semiconductor device includes: a plurality of transistors on a substrate, each transistor of the plurality of transistors including a source region, a drain region, a gate structure, a polarization modulation portion, and a polarization layer. The polarization modulation portion of each of the plurality of transistors is on the polarization layer, the plurality of transistors includes a first transistor having a first threshold voltage that has a first fixed value, and the plurality of transistors includes a second transistor having a second threshold voltage that has a second fixed value different from the first fixed value.

The present disclosure generally relates to semiconductor devices in an integrated circuit (IC) that have different threshold voltages. In an example, an IC includes a semiconductor substrate, a channel layer, a barrier layer, a first semiconductor device, and a second semiconductor device. The channel layer is on the semiconductor substrate, and the channel layer includes a gallium nitride (GaN) material. The barrier layer is on the channel layer. The first semiconductor device is on the semiconductor substrate. The first semiconductor device includes a first terminal over the barrier layer, and the first semiconductor device has a first threshold voltage. The second semiconductor device is on the semiconductor substrate. The second semiconductor device includes a second terminal over the barrier layer, and the second semiconductor device has a second threshold voltage different from the first threshold voltage. The first and second threshold voltages are both positive or negative voltages.

A semiconductor device includes a semiconductor substrate; a source electrode, a gate electrode, and a drain electrode on the semiconductor substrate; a staircase dielectric structure on the semiconductor substrate and laterally between the gate electrode and the drain electrode; and a metal layer on the staircase dielectric structure. The staircase dielectric structure includes a first dielectric layer on the semiconductor substrate, a first etch-stop layer on the first dielectric layer, and a second dielectric layer on the first etch-stop layer, where the first dielectric layer has a first lateral dimension greater than a second lateral dimension of the second dielectric layer. The metal layer includes a first field plate on at least a first region of the first dielectric layer and a second field plate on at least a second region of the second dielectric layer.

This disclosure provides semiconductor device including a first transistor with a first gate terminal, a first source terminal, and the first drain terminal, the first transistor being a depletion mode transistor and including a plurality of two-dimensional carrier channels of a conductivity type being one of a n-type or a p-type conductivity. The semiconductor device also includes a second transistor with a second gate terminal, a second source terminal, and a second drain terminal, the second transistor being an enhancement mode transistor, a gate-source interconnect forming an electrical connection between the first gate terminal and the second source terminal, and a drain-source interconnect forming an electrical connection between the first source terminal and the second drain terminal. The first transistor and the second transistor are fabricated on the same wafer or substrate.

This disclosure provides semiconductor device including a first transistor with a first gate terminal, a first source terminal, and the first drain terminal, the first transistor being a depletion mode transistor and including a plurality of two-dimensional carrier channels of a conductivity type being one of a n-type or a p-type conductivity. The semiconductor device also includes a second transistor with a second gate terminal, a second source terminal, and a second drain terminal, the second transistor being an enhancement mode transistor, a gate-source interconnect forming an electrical connection between the first gate terminal and the second source terminal, and a drain-source interconnect forming an electrical connection between the first source terminal and the second drain terminal. The first transistor and the second transistor are fabricated on the same wafer or substrate.

Novel NEDMOS and/or LDMOS FET integrated circuit structures that reduce or eliminate the floating body effect by reducing the built-in voltage Vbi of the device. Reduction of Vbi includes adding a source-side structure that includes a Vbi Reduction Material (VRM) layer. VRM has a bandgap less than the bandgap of Si and, for an N-type device, a valence band that is higher than the valence band of the body material. The low Vbi of the VRM layer on the source-side of a MOSFET device that would otherwise exhibit a floating body effect allows significantly freer movement of holes from the body of the device towards the source region, thus increasing body hole collection efficiency, and significantly reduces the floating body effect.