A semiconductor device is provided that includes a deep trench defining an active region, and a fin-type pattern protruding within the active region. The fin-type pattern having a lower portion, an upper portion of a narrower width than the lower portion, and a first stepped portion formed at a boundary between the upper portion and the lower portion. The device also includes a first field insulating film surrounding the lower portion and a second field insulating film formed on the first field insulating film and partially surrounding the upper portion.

A semiconductor device includes a substrate including a first trench, a first fin pattern on the substrate that is defined by the first trench, a gate electrode on the substrate, and a field insulating layer on the substrate. The first fin pattern includes an upper part on a lower part. The first fin pattern includes a first sidewall and a second sidewall opposite each other. The first sidewall is concave along the lower part of the first fin pattern. The second sidewall is tilted along the lower part of the first fin pattern. The field insulating layer surrounds the lower part of the first fin pattern. The gate electrode surrounds the upper part of the first fin pattern.

Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.

Embodiments herein describe dummy gates disposed over a portion of a fin in finFETs. That is, instead of separating the dummy gates from the finFET structure, the fins may be extended and covered, at least partially, by the dummy gates. An insulative material is disposed between the dummy gate and the fin in order to form a decoupling capacitor. In one embodiment, the dummy gate overlaps a portion of the fin that is held at a voltage rail. Moreover, the dummy gate may be coupled to a different (e.g., opposite) voltage rail than rail coupled to the fin. For example, if the fin is coupled to V.sub.HIGH then the dummy gate is coupled to V.sub.LOW, or vice versa. Thus, the capacitor formed using the fin and the dummy gate provides a decoupling capacitance between the power sources generating the voltage rails (i.e., V.sub.HIGH and V.sub.LOW).

A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners. There is a gate stack on the channel region of the one or more semiconductor fins.

An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.

A semiconductor device includes a substrate, a semiconductor fin, a gate stack, and an epitaxy structure. The semiconductor fin is disposed in the substrate. A portion of the semiconductor fin is protruded from the substrate. The gate stack is disposed over the portion of the semiconductor fin protruded from the substrate. The epitaxy structure is disposed on the substrate and adjacent to the gate stack. The epitaxy structure has a top surface facing away the substrate, and the top surface has at least one curved portion having a radius of curvature ranging from about 5 nm to about 20 nm.

An insulator is formed over a substrate, an opening is formed in the insulator, and an oxide semiconductor is formed in the opening. Then, part of the insulator is removed to expose a side surface of the oxide semiconductor.