Methods and semiconductor structures are provided. A method according to the present disclosure includes depositing a top epitaxial layer over a substrate, forming a fin structure from the top epitaxial layer and a portion of the substrate, recessing a source/drain region of the fin structure to form a source/drain recess, conformally depositing a semiconductor layer over surfaces of the source/drain recess, etching back the semiconductor layer to form a diffusion stop layer over a bottom surface of the source/drain recess, depositing a first epitaxial layer over the diffusion stop layer and sidewalls source/drain recess, depositing a second epitaxial layer over the first epitaxial layer, and depositing a third epitaxial layer over the second epitaxial layer. A germanium concentration of the diffusion stop layer is greater than a germanium concentration of the top epitaxial layer or a germanium concentration of the first epitaxial layer.

A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.

In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.

A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50 C. to 100 C., and a duration of the baking process is between 5 seconds to 120 seconds.

A semiconductor device includes a substrate with first through fourth regions and an interlayer insulating layer disposed thereon that has first through fourth trenches corresponding to the first through fourth regions. Each of the trenches has a corresponding gate insulating layer and gate electrode that includes a lower conductive layer and an upper gate electrode. The lower conductive layers in each trench may have different thicknesses from each other and may be formed of the same conductive material. The thickest of the four lower conductive layers may have the corresponding upper gate electrode cover its uppermost surface.

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.