A method for forming a semiconductor device includes forming first fins from a first semiconductor material and second fins from a second semiconductor material and encapsulating the first fins and the second fins with a protective dielectric. Semiconductor material between the first fins and the second fins is etched to form trenches. A dielectric fill is employed to fill up the trenches, between the first fins and between the second fins. The first semiconductor material below the first fins and the second semiconductor material below the second fins are oxidized with the first and second fins being protected by the protective dielectric. Fins in an intermediary region between the first fins and the second fins are oxidized to form dummy fins in the intermediary region to maintain a substantially same topology across the device.

An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

A method includes providing a substrate having a mesa, forming a first opening in the mesa, the first opening being surrounded by first inner sidewalls of the mesa exposed by the first opening. The method further includes etching from a first one of the first inner sidewalls of the mesa to form a first vertical recess, the first vertical recess having a wide end and a narrow end, with the narrow end defining a first vertically recessed channel region, and forming a first gate structure over the first vertically recessed channel region.

Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

An integrated circuit product includes an NFET FinFET device having a first fin that is made entirely of a first semiconductor material and a PFET FinFET device that includes a second fin having an upper portion and a lower portion, wherein the lower portion is made of the first semiconductor material and the upper portion is made of a second semiconductor material that is different from the first semiconductor material. A silicon nitride liner is positioned on and in contact with the lower portion of the second fin, wherein the silicon nitride liner is not present on or adjacent to the upper portion of the second fin or on or adjacent to any portion of the first fin.

A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a plurality of fin-shaped structures thereon; forming a first shallow trench isolation (STI) between the fin-shaped structures and a second STI around the fin-shaped structures; removing part of the fin-shaped structures; and removing part of the first STI so that the top surfaces of the fin-shaped structures are higher than the top surface of the first STI and lower than the top surface of the second STI.

A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.