A semiconductor structure includes a nanofog oxide adhered to an inert 2D or 3D surface or a weakly reactive metal surface, the nanofog oxide consisting essentially of 0.5-2 nm Al.sub.2O.sub.3 nanoparticles. The nanofog can also consists of sub 1 nm particles. Oxide layers can be formed on the nanofog, for example a bilayer stack of Al.sub.2O.sub.3—HfO.sub.2. Additional examples are from the group consisting of ZrO.sub.2, HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2, ZrTiO.sub.2, HfTiO.sub.2, La.sub.2O.sub.3, Y.sub.2O.sub.3, Ga.sub.2O.sub.3, GdGaOx, and alloys thereof, including the ferroelectric phases of HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2. The structure provides the basis for various devices, including MIM capacitors, FET transistors and MOSCAP capacitors.

A memory includes: a substrate, having a plurality of active regions arranged in an array and a plurality of word lines extending in a first direction, the active regions being inclined at a preset angle to the word lines, the active region having at least one access transistor; a plurality of bit lines, extending in a second direction perpendicular to the first direction; magnetic tunnel junctions, one end of the magnetic tunnel junction is electrically connected to one of bit lines and another end of the magnetic tunnel junction is electrically connected to two access transistors, the two access transistors electrically connected to the magnetic tunnel junction being located in two adjacent active regions, respectively.

Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a third terminal is coupled to the first device, wherein the first terminal and second terminal are independently coupled to the first device and second device respectively. The third terminal can be coupled to the second device. The first terminal, the second terminal, and third terminal and couple components included in the multi terminal stack to components not included in the multi terminal stack.

A magnetic memory device including a substrate; a first and second magnetic pattern stacked on the substrate; a tunnel barrier pattern between the first and second magnetic pattern; a bottom electrode between the substrate and the first magnetic pattern; a seed pattern between the bottom electrode and the first magnetic pattern; and a diffusion barrier pattern between the bottom electrode and the seed pattern, wherein a bottom surface of the at least one diffusion barrier pattern is in contact with a top surface of the bottom electrode, and a top surface of the at least one diffusion barrier pattern is in contact with a bottom surface of the seed pattern, the at least one diffusion barrier pattern includes a non-magnetic metal, or an alloy of the non-magnetic metal and a non-metal element, and the non-magnetic metal includes Ta, W, Nb, Ti, Cr, Zr, Hf, Mo, Al, Mg, or V.

A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.

A method includes providing a structure having a memory region and a logic region; a first metal layer and a dielectric barrier layer over the first metal layer in both the memory region and the logic region; a first dielectric layer over the dielectric barrier layer; multiple magnetic tunneling junction (MTJ) devices over the first metal layer, the dielectric barrier layer, and the first dielectric layer; and a second dielectric layer over the first dielectric layer and the MTJ devices. The first dielectric layer, the MTJ devices, and the second dielectric layer are in the memory device region and not in the logic device region. The method further includes depositing an extreme low-k (ELK) dielectric layer using FCVD over the memory region and the logic region; and buffing the ELK dielectric layer to planarize a top surface of the ELK dielectric layer.

A technique relates to an integrated circuit (IC). Pillars of a set of memory elements are formed. A bilayer dielectric is formed between the pillars, the bilayer dielectric having an upper dielectric material formed on a lower dielectric material without requiring an etch of the lower dielectric material prior to forming the upper dielectric material, thereby preventing a void in the bilayer dielectric, the lower dielectric material including one or more flowable dielectric materials.

An approach providing a semiconductor structure that provides a self-leveling, flowable, dielectric material for a gap fill material between vertical structures in many emerging non-volatile memory devices that are being formed with vertical structures for increasing memory device density. The semiconductor structure provides a flat dielectric surface between a plurality of contacts in a back end of the line metal layer in both the memory region and in the logic region of the semiconductor structure. The semiconductor structure includes a first portion of the plurality of contacts that each connect to a pillar-based memory device in an array of pillar-based memory devices. The first portion of the contacts that each connect to a pillar-based memory device in the array of memory devices reside in a conventional interlayer dielectric material under the self-leveling dielectric material. The flowable, self-leveling material provides a flat dielectric surface during contact formation.

Apparatus and associated methods relate to a magnetoresistive sensor element with synthetic antiferromagnetic biasing structure separated, by a non-magnetic tuning spacer, from a free ferromagnetic layer of a TMR/GMR sensor. The synthetic antiferromagnetic biasing structure includes first and second ferromagnetic layers separated from one another by a synthetic antiferromagnetic spacer. The synthetic antiferromagnetic biasing structure is biased during manufacture and pinned via exchange coupling with an adjacent antiferromagnetic layer. The synthetic antiferromagnetic biasing structure biases the free ferromagnetic layer via tuned exchanged coupling via relative proximity controlled by thickness of the non-magnetic tuning spacer.

A method for fabricating a semiconductor device including a plurality of memory cells. The method includes: forming a first electrode layer; forming an initial Si-containing layer over the first electrode layer; performing a radical oxidation process to covert a first portion of the initial Si-containing layer into an oxide layer including silicon dioxide (SiO.sub.2) and form a Si-containing layer under the oxide layer by using a second portion of the initial Si-containing layer; and incorporating a dopant into the oxide layer by an ion implantation process to form a selector pattern.