A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.

Some examples relate to an integrated circuit. The integrated circuit comprises a semiconductor substrate, a bottom electrode over the substrate, a circular magnetic tunneling junction (MTJ) disposed over an upper surface of bottom electrode, and a circular top electrode disposed over an upper surface of the magnetic tunneling junction. The circular top electrode is concentric to the circular magnetic tunneling junction, and a diameter of the circular magnetic tunneling junction is smaller than 60 nm or smaller than 30 nm.

A memory device including an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a vertical stack containing a bottom electrode, a memory element, a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.

A memory array and a method for forming the memory array are disclosed. The memory array includes memory elements, selectors and conductive vias. Each selector includes two pairs of fin structures. The conductive vias are electrically coupled to the two pairs of fin structures of the selectors.

A magnetic sensor comprising: an application specific integrated circuit (ASIC); an insulating protective film formed on a surface of the ASIC; a substrate film formed on the insulating protective film; and a magnetic field detection element formed on the substrate film, the magnetic field detection element including two magnetic wires on the substrate film, a detection coil surrounding the two magnetic wires, two electrodes coupled to the two magnetic wires for wire energization, and two electrodes coupled to the coil for coil voltage detection.

A method for manufacturing a magnetic random access memory element having increased retention and low resistance area product (RA). A MgO layer is deposited to contact a magnetic free layer of the memory element. The MgO layer is deposited in a sputter deposition chamber using a DC power and a Mg target to deposit Mg. The deposition of Mg is periodically stopped and oxygen introduced into the deposition chamber. This process is repeated a desired number of times, resulting in a multi-layer structure. The resulting MgO layer provides excellent interfacial perpendicular magnetic anisotropy to the magnetic free layer while also having a low RA.

A multilayered magnetic free layer structure is provided that includes a first magnetic free layer and a second magnetic free layer separated by a non-magnetic layer in which the second magnetic free layer is composed of a M.sub.1/M.sub.2 superlattice structure or a M.sub.1/M.sub.2 multilayer structure, wherein M.sub.1 is a first magnetic metal selected from the group consisting of cobalt (Co), iron (Fe) and alloys thereof, and M.sub.2 is a second magnetic metal selected from the group consisting of platinum (Pt), palladium (Pd), nickel (Ni), rhodium (Rh), iridium (Jr), rhenium (Re) and alloys thereof.

The present disclosure generally relates to a Wheatstone bridge array that has four resistors. Each resistor includes a plurality of TMR films. Each resistor has identical TMR films. The TMR films of two resistors have reference layers that have an antiparallel magnetic orientation relative to the TMR films of the other two resistors. To ensure the antiparallel magnetic orientation, the TMR films are all formed simultaneously and annealed in a magnetic field simultaneously. Thereafter, the TMR films of two resistors are annealed a second time in a magnetic field while the TMR films of the other two resistors are not annealed a second time.

A perpendicular magnetic tunnel junction is disclosed wherein a metal insertion (MIS) layer is formed within a free layer (FL), a partially oxidized Hk enhancing layer is on the FL, and a nitride capping layer having a buffer layer/nitride layer (NL) is on the Hk enhancing layer to provide an improved coercivity (Hc)/switching current (Jc) ratio for spintronic applications. Magnetoresistive ratio is maintained above 100%, resistance×area (RA) product is below 5 ohm/μm.sup.2, and thermal stability to 400° C. is realized. The FL comprises two or more sub-layers, and the MIS layer may be formed within at least one sub-layer or between sub-layers. The buffer layer is used to prevent oxygen diffusion to the NL, and nitrogen diffusion from the NL to the FL. FL thickness is from 11 Angstroms to 25 Angstroms while MIS layer thickness is preferably from 0.5 Angstroms to 4 Angstroms.