A perpendicular magnetic tunnel junction is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to provide thermal stability to 400° C. Insertion of an oxidation control layer (OCL) such as Mg and a magnetic moment tuning layer (MMTL) like Mo or W enables FL thickness to be reduced below 10 Angstroms while providing sufficient PMA for a switching voltage substantially less than 500 mV at a 10 ns pulse width and 1 ppm defect rate. Magnetoresistive ratio is ≥1, and resistance×area (RA) product is below 5 ohm-μm.sup.2. Embodiments are provided where MMTL and OCL materials interface with each other, or do not contact each other. Each of the MMTL and OCL materials may be deposited separately, or at least one is co-deposited with the FL.

A method of forming a magnetic random access memory (MRAM) device includes forming a bottom electrode layer over a substrate including an inter-metal dielectric (IMD) layer having a metal line therein; forming a barrier layer over the bottom electrode layer; forming a magnetic tunnel junction (MTJ) layer stack over the bottom electrode layer; forming a dielectric layer over the MTJ layer stack; forming an opening in the dielectric layer to expose the barrier layer; filling the opening in the dielectric layer with a top electrode; after filling the opening in the dielectric layer with the top electrode, etching the dielectric layer to expose the barrier layer; and patterning the MTJ layer stack to form an MTJ stack that exposes the bottom electrode layer.

A spin valve magnetoresistance element has an even number of free layer structures for which half has an antiferromagnetic coupling and the other half has a ferromagnetic coupling with respect to associated pinned layers. The different couplings are the result of an even number different spacer layers having respective different thicknesses.

A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure. The first dummy pattern structure is formed on both edge portions in the first direction, and the second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of the lower cell structure thereunder, and the second dummy pattern structure is formed on both edge portions in the second direction, and the first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of the lower cell structure thereon. Failures of the variable resistance memory device due to the etch residue may decrease.

A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

An embodiment of the present invention is a method of manufacturing a perpendicular MTJ device which includes: a first stacked structure including a pair of CoFeB layers sandwiching an MgO layer; and a second stacked structure including a multilayer, the method comprising the steps of: forming one of the first and second stacked structures on a substrate; inspecting a property of the substrate with the one of the first and second stacked structures formed thereon while exposing the substrate to the atmosphere; and forming another one of the first and second stacked structures on the substrate with the one of the first and second stacked structures formed thereon.

A method for forming a perpendicular magnetization type magnetic tunnel junction element includes forming a tunnel barrier layer on a first magnetic layer of a workpiece, cooling the workpiece on which the tunnel barrier layer is formed, and forming a second magnetic layer on the tunnel barrier layer after the cooling.

A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.

The disclosed technology includes an electronic device. The electronic device includes a semiconductor memory, and the semiconductor memory includes a variable resistance element that exhibits different resistance states for storing different data and is structured to include a planar shape including two curved potions of different curvatures.

The present disclosure relates to a method of forming an integrated chip. The method includes forming an ILD layer over a memory device over a substrate. A hard mask structure is formed over the ILD layer and a patterning structure is formed over the hard mask structure. The hard mask structure has sidewalls defining a first opening directly over the memory device and centered along a first line perpendicular to an upper surface of the substrate. The patterning structure has sidewalls defining a second opening directly over the memory device and centered along a second line parallel to the first line. The second line is laterally offset from the first line by a non-zero distance. The ILD layer is etched below an overlap of the first and second openings to define a top electrode via hole. The top electrode via hole is with a conductive material.