A magnetoresistance element can have a substrate; a ferromagnetic seed layer consisting of a binary alloy of NiFe; and a first nonmagnetic spacer layer disposed under and directly adjacent to the ferromagnetic seed layer and proximate to the substrate, wherein the first nonmagnetic spacer layer is comprised of Ta or Ru. A method fabricating of fabricating a magnetoresistance element can include depositing a seed layer structure over a semiconductor substrate, wherein the depositing the seed layer structure includes depositing at least a ferromagnetic seed layer over the substrate. The method further can further include depositing a free layer structure over the seed layer structure, wherein the depositing the ferromagnetic seed layer comprises depositing the ferromagnetic seed layer in the presence of a motion along a predetermined direction and in the presence of a predetermined magnetic field having the same predetermined direction.

An integrated circuit includes a magnetic OTP memory array formed of multiple magnetic OTP memory cells having an MTJ stack with a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer, and a second electrode. When a voltage is applied across the magnetic OTP memory cell, the resistance of the MTJ stack and the gating transistor form a voltage divider to apply a large voltage across the MTJ stack to breakdown the tunnel barrier to short the fixed layer to the free layer. The integrated circuit has multiple MRAM arrays configured such that each of the multiple MRAM arrays have performance and density criteria that match MOS transistor based memory including SRAM, DRAM, and flash memory. The integrated circuit may include a functional logic unit connected with the magnetic OTP memory arrays and the MRAM arrays for providing digital data storage.

An interposer for an integrated circuit includes a first side and a second side. The interposer includes a substrate and a via disposed in the substrate. A first electrical contact is disposed on the first side. A second electrical contact is disposed on the second side and electrically connected to the via. The interposer also includes a multiple-time programmable (“MTP”) element electrically connected to the first electrical contact and/or the via.

A storage device includes a first electrode, a second electrode, a storage element, a spacer and a barrier structure. The second electrode is opposite to the first electrode. The storage element is disposed between the first electrode and the second electrode. The spacer is formed on a sidewall of the second electrode, and the spacer has a notch positioned on a top surface of the spacer. The barrier structure is embedded in a lateral of the spacer, and the barrier structure has a top extending upwards past a bottom of the notch. In addition, a method of manufacturing the storage device is disclosed as well.

Magnetic memory structure and memory device are provided. A magnetic memory structure includes a metal layer, a first magnetic tunnel junction, and a second magnetic tunnel junction. The metal layer includes a first contact region and a second contact region. Electrical resistivity of at least a first part of the first contact region is different than electrical resistivity of the second contact region. The first magnetic tunnel junction is disposed on the metal layer. The first magnetic tunnel junction includes a first free layer in contact with the first contact region of the metal layer. The second magnetic tunnel junction is disposed on the metal layer. The second magnetic tunnel junction includes a second free layer in contact with the second contact region of the metal layer.

According to an aspect, there is provided a method of forming a magnetic tunneling junction (MTJ) device, including: forming a layer stack including an MTJ layer structure and a spin-orbit torque (SOT) layer below the MTJ layer structure; forming a first etch mask over the layer stack, the first etch mask including a first mask line extending in a first horizontal direction; patterning the layer stack to form an MTJ line extending in the first horizontal direction, the patterning including etching while the first etch mask masks the layer stack, and stopping etching on or above the SOT-layer; forming sidewall spacers on one or both sides of the MTJ line; while the sidewall spacers mask the SOT-layer, etching the SOT-layer to form a patterned layer stack including the MTJ line and a first patterned SOT-layer; forming a second etch mask over the patterned layer stack, the second etch mask including a second mask line extending in a second horizontal direction across the MTJ line; and patterning the patterned layer stack to form a twice patterned SOT-layer, the twice patterned SOT-layer including an SOT-line extending in the second horizontal direction, and to form an MTJ pillar on the SOT-line, the patterning including etching while the second etch mask masks the patterned layer stack.

A MRAM-based magnetic device including an electrical interconnecting device including: a magnetic tunnel junction; a strap portion electrically connecting a lower end of the magnetic tunnel junction; a current line portion electrically connecting an upper end of the magnetic tunnel junction; an upper metallic stud electrically connecting a lower metallic stud through a via; the strap portion being in direct electrical contact with the via, such that a current passing in the magnetic tunnel junction flows directly between the strap portion and the via and between the via and the lower metallic stud or the upper metallic stud.

The invention discloses a memory fabrication method. The memory fabrication method includes forming a plurality of gate electrode lines to respectively form a plurality of gates of a plurality of data storage cells, and forming a plurality of conductive lines. The plurality of data storage cells are arranged in an array. Each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines. Each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines.

A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

A method for manufacturing a memory device includes forming a via trench in a substrate and forming a via in the via trench. A lower portion of the via includes a first metal and an upper portion of the via includes a second metal that is different from the first metal. The method further includes forming a magnetic tunneling junction over the via and forming a top electrode over the magnetic tunneling junction.