Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a fixed layer that is magnetic and a tunnel barrier layer overlying the fixed layer, where the tunnel barrier layer is non-magnetic. A total free layer overlies the tunnel barrier layer, where the total free layer includes a plurality of individual free layers, wherein each of the plurality of individual free layers includes one or more of cobalt, iron, or boron, and where each of the plurality of individual free layers is magnetic. At least one of the plurality of individual free layers includes an atomic ratio of cobalt to iron that is from about 0.9/1 to about 1.1/1.

The invention comprises a novel composite seed structure (CSS) having lattice constant matched crystalline structure with the Co layer in above perpendicular magnetic pinning layer (pMPL) so that an excellent epitaxial growth of magnetic super lattice pinning layer [Co/(Pt, Pd or Ni)].sub.n along its FCC (111) orientation can be achieved, resulting in a significant enhancement of perpendicular magnetic anisotropy (PMA) for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.

A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

A method of manufacturing an electronic device including a semiconductor memory is provided. The method may include forming a material layer for forming a variable resistance element over a substrate, forming a metal layer over the material layer, forming a mask pattern over the metal layer, forming a metal layer pattern by etching the metal layer using the mask pattern as an etch barrier, performing a surface treatment on the metal layer pattern, and etching the material layer using the metal layer pattern and the metal compound layer as an etch barrier to form a variable resistance element having an external side aligned with an external side of the metal compound layer. An external part of the metal layer pattern may be transformed into a metal compound layer. The metal compound layer may have a low etch rate as an etch barrier.

A device manufacturing apparatus and manufacturing method of a magnetic device. The device manufacturing apparatus can include a substrate holding portion configured to hold a substrate, an ion source, an anode disposed in a housing of the ion source, and a cathode disposed outside the housing of the ion source. A first opening can be disposed in a portion of the housing such the anode is exposed to a region between the anode and the substrate holding portion. The ion source can be configured to generate an ion beam with which the substrate is irradiated. A first structure can be disposed between the ion source and the substrate holding portion. The first structure can have a first through hole through which the ion beam can pass. The first structure can include a conductor, and an opening dimension of the first through hole can be equal to or larger than an opening dimension of the first opening.

A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

An illustrative memory cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) structure positioned above the bottom electrode and below the top electrode. In this example, the MTJ structure includes a first ferromagnetic material layer positioned above the bottom electrode, a non-magnetic insulation layer positioned above the first ferromagnetic material layer and a second ferromagnetic material layer positioned on the non-magnetic insulation layer, wherein there is a curved, non-planar interface between the non-magnetic insulation layer and the ferromagnetic material layer.

The invention disclosed a method to make hard mask with ultra-small dimensions for fabricating integrated nonvolatile random access memory, for example, a magnetic-random-access memory (MRAM), a resistance random access memory (RRAM), a phase change random access memory (PCRAM), or a ferroelectric random access memory (FRAM). Instead of directly depositing hard mask material on top of the memory film stack element, we first make ultra-small VIA holes on a pattern transfer molding (PTM) layer using a reverse memory mask, then fill in the hard mask material into the VIA holes within the PTM material. Ultra-small hard mask pillars are formed after removing the PTM material. To improve the adhesion of the hard mask pillars with the underneath memory stack element, a hard mask sustaining (HMS) layer is added below PTM. Using PTM as the mask, array of HM ditches are first formed in the HMS layer to implant a hard mask seed in it before filling the main portion of the hard mask in the PTM VIAs. For a better formation of the HMS ditches, an etching stop layer can be used below the HMS layer to allow some over-etch of the HMS without punching into the memory film stack. Due to a better materials adhesion between HMS and the hard mask, a stronger hard mask array can be formed.

An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

A spin-transfer-torque magnetoresistive memory comprises apparatus and method of manufacturing a three terminal magnetoresistive memory element having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell comprises a bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current along the SHE-metal layer by applying a low write current.