A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.

In various embodiments, photovoltaic devices incorporate discontinuous passivation layers (i) disposed between a thin-film absorber layer and a partner layer, (ii) disposed between the partner layer and a front contact layer, and/or (iii) disposed between a back contact layer and the thin-film absorber layer.

A microchip structure and a method for manufacturing thereof are provided. The microchip structure comprises a target integrated circuit (TIC) comprising a first surface and a first power contact at a first location on the first surface of the TIC, the TIC further comprising a second power contact at a second location on the first surface of the TIC; a plurality of photovoltaic (PV) diodes deposited on a first surface of a transparent substrate, each of the PV diodes having an anode coupled to an anode contact and a cathode coupled to a cathode contact, the transparent substrate is transparent to an electromagnetic frequency to which the PV diodes are sensitive; the cathode contact of a first PV diode of the PV diodes is bonded to the first power contact and the anode contact of a second PV diode of the PV diodes is bonded to the second power contact.

A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.

A method for use in forming a photovoltaic device includes forming a doped semiconductor layer on a surface of a semiconductor substrate and forming a metal film on the doped semiconductor layer. A patterned etched resist is formed on the metal film and a dielectric layer is formed on the doped semiconductor layer and the etched resist. A laser having a wavelength absorbable by the patterned etch resist is applied through the dielectric layer to the patterned etch resist to remove the patterned etch resist.

A high efficiency configuration for a solar cell module comprises solar cells arranged in an overlapping shingled manner and conductively bonded to each other in their overlapping regions to form super cells, which may be arranged to efficiently use the area of the solar module.

A solar cell is disclosed, which includes a crystalline semiconductor substrate of a first conductive type, a front doped layer on a front surface of the semiconductor substrate and forming a hetero junction with the semiconductor substrate, a back doped layer on a back surface of the semiconductor substrate and forming a hetero junction with the semiconductor substrate, a front transparent conductive layer on the front doped layer, a back transparent conductive layer under the back doped layer. One of the front doped layer and the back doped layer has a second conductive type opposite to the first conductive type to form a p-n junction with the semiconductor substrate, and the other of the front doped layer and the back doped layer has the first conductive type. A planar area of the front transparent conductive layer is larger than a planar area of the back transparent conductive layer.

Discussed is a solar cell including a single crystalline semiconductor substrate having a first transparent conductive oxide layer positioned on a non-single crystalline emitter layer; a second transparent conductive oxide layer positioned over a rear surface of the single crystalline semiconductor substrate; a first electrode part including a first seed layer directly positioned on the first transparent conductive oxide layer; and a second electrode part including a second seed layer directly positioned on the second transparent conductive oxide layer, wherein the first transparent conductive oxide layer and the first seed layer have different conductivities, and wherein the second transparent conductive oxide layer and the second seed layer have different conductivities.

A power generating system comprising: a plurality of power generating units coupled in parallel; a power collecting device for collecting electric power output from the plurality of power generating units; and wirings for coupling the plurality of power generating units and the power collecting device. A ratio of a conductor diameter to a predetermined length of each of the wirings is defined as a reference ratio. A value obtained by multiplying the reference ratio, a number of the wirings, and a loss generated by a specific wiring together is subtracted from a value obtained by multiplying a predetermined number of wirings for adjustment by a ratio of a conductor diameter to a length of the specific wiring. A total of the ratios of the conductor diameters to the lengths of the predetermined number of the wirings for adjustment is determined as a value less than the subtracted value.

The present specification relates to a conductive structure body and a method for manufacturing the same.