A three-dimensional semiconductor device may include a substrate including a cell array region and a contact region, a stack structure including interlayer dielectric layers and gate electrodes, a source structure, and a mold structure between the substrate and the stack structure. First vertical channel structures are on the cell array region in vertical channel holes. Each of the first vertical channel structures may include a first barrier pattern, a data storage pattern, and a vertical semiconductor pattern, which are sequentially layered on an inner side surface of one of the vertical channel holes. The mold structure may include a first buffer insulating layer, a first semiconductor layer, a second buffer insulating layer, and a second semiconductor layer sequentially stacked on the substrate. The source structure may be in physical contact with a portion of a side surface of the vertical semiconductor pattern.

A semiconductor storage device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked along a stacking direction, and a plurality of first pillars extending in the stacked body along the stacking direction to form memory cells at intersections with at least some of the plurality of conductive layers. The stacked body includes a stair portion in which the plurality of conductive layers are stacked in a stepped manner at a position separated from the plurality of first pillars in a first direction intersecting the stacking direction. At least a lowermost insulating layer of the plurality of insulating layers has at least one bending portion bent in the stacking direction at an end of the plurality of conductive layers in the stair portion along the first direction.

According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.

Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. The device includes a substrate, a cell array structure provided on the substrate to include a plurality of stacked electrodes spaced apart from each other, an uppermost one of the electrodes being a first string selection line, a vertical channel structure provided to penetrate the cell array structure and connected to the substrate, a conductive pad provided in an upper portion of the vertical channel structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a cutting structure penetrating the first string selection line. The cutting structure penetrates a portion of the conductive pad. A bottom surface of the bit line contact includes first and second bottom surfaces in contact with the conductive pad and the cutting structure, respectively.

A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure, the cell array structure including a stack structure having alternating interlayer dielectric layers and gate electrodes, a first insulating layer covering the stack structure, and a second substrate on the stack structure and the first insulating layer, the stack structure being between a bottom surface of the second substrate and the peripheral circuit structure, a second insulating layer on the cell array structure, a first penetration contact penetrating the first insulating layer, the second substrate, and the second insulating layer, and a second penetration contact penetrating the first insulating layer and the second insulating layer, the second penetration contact being spaced apart from the second substrate, and the first and second penetration contacts having widths decreasing with increasing distance from the first substrate.

A semiconductor device including: a first silicon layer including a first single crystal silicon and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, a connection path from the fifth metal layer to the second metal layer, where the connection path includes a via disposed through the second level, where the via has a diameter of less than 450 nm, where the fifth metal layer includes a global power distribution grid, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

A semiconductor device including a peripheral circuit structure on a substrate, a horizontal layer on the peripheral circuit structure, an electrode structure including electrodes on the horizontal layer, the electrodes including pads arranged in a stepwise shape, a planarization insulating layer covering the pads, a contact plug penetrating the planarization insulating layer and coupled to one of the pads, a penetration via penetrating the planarization insulating layer and coupled to the peripheral circuit structure, and a vertical conductive structure between the electrode structure and the penetration via may be provided. The vertical conductive structure may have a bottom surface located at a level that is higher than a top surface of the horizontal layer and is lower than a bottom end of the contact plug.

A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.