A memory die includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures extending through the alternating stack, and each of the memory stack structures includes a respective vertical semiconductor channel and a respective memory film, drain regions located at a first end of a respective one of the vertical semiconductor channels, and a source layer having a first surface and a second surface. The first surface is located at a second end of each of the vertical semiconductor channels, and a semiconductor wafer is not located over the second surface of the source layer.

The integrated circuit of a non-volatile memory of the electrically erasable and programmable type includes memory cells, each memory cell having a state transistor including a gate structure comprising a control gate and a floating gate disposed on a face of a semiconductor well, as well as a source region and a drain region in the semiconductor well. The drain region includes a first capacitive implant region positioned predominantly under the gate structure and a lightly doped region positioned predominantly outside the gate structure. The source region includes a second capacitive implant region positioned predominantly outside the gate structure, the source region not including a lightly doped region.

A semiconductor device includes a first structure including a substrate, circuit devices, a lower interconnection structure electrically connected to the circuit devices, and a second structure on the first structure. The second structure includes a conductive plate layer; gate electrodes on the conductive plate layer and extending in a first direction; separation regions penetrating through the gate electrodes and extending in the first direction; channel structures penetrating through the gate electrodes and respectively including a channel layer; through-contact plugs spaced apart from the gate electrodes and extending in the vertical direction to be electrically connected to the lower interconnection structure of the first structure; first and second contacts electrically connected to the channel layer and the through-contact plugs, respectively; bitlines electrically connecting at least one of each of the first and second contacts to each other; and dummy contacts connected to the bitlines and spaced apart from the through-contact plugs.

In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of word lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The gate electrode includes a metal, and the gate dielectric has a thickness between 1.8 nm and 10 nm.

In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of bit lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

A semiconductor memory device, and a method of manufacturing the same, includes a first stack and a second stack stacked on a semiconductor substrate in a cell region of the semiconductor memory device and a slit region of the semiconductor memory device adjacent to the cell region. The semiconductor memory device also includes a plurality of cell plugs at least partially passing through the second stack and the first stack of the cell region and extending in a vertical direction, a slit at least partially passing through the second stack and the first stack of the slit region, and a protective pattern disposed between the slit and dummy cell plugs adjacent to the slit among the plurality of cell plugs.

A semiconductor memory device may include a substrate, a plurality of lower electrodes on the substrate, and a support structure. The plurality of lower electrodes may extend in a first direction perpendicular to a top surface of the substrate. The support structure may have a flat panel shape. The support structure may contact a side surface of the plurality of lower electrodes and may support the plurality of lower electrodes. The support structure may include a plurality of openings. The support structure may include a first part and a second part. The first part may include the plurality of openings repeated by a first pitch. The second part may include the plurality of openings repeated by a second pitch that is different from the first pitch.

Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

A semiconductor memory includes electrode structures that each includes horizontal electrodes stacked on each other a substrate, vertical electrodes between the electrode structures and extending along the horizontal electrodes, first contacts connected to the horizontal electrodes at end portions of the electrode structures, second contacts connected to upper portions of the vertical electrodes, and a first interconnection structure connected to top surfaces of the second contacts. The first interconnection structure includes first and second sub-interconnection lines. The sub-interconnection lines extend in a first direction and contact the top surfaces of the second contacts. The second sub-interconnection lines extended in a second direction crossing the first direction and contact the first sub-interconnection lines.