A semiconductor device and the method of manufacturing the same are provided. The semiconductor device includes a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.

A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

A semiconductor memory device may include a pillar, a gate and at least one ferroelectric layer. The pillar may include a source, a drain and a channel region. The drain may be arranged over the source. The channel region may be arranged between the source and the drain. The gate may be formed on an outer surface of the pillar. The ferroelectric layer may be interposed between the pillar and the gate.

The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices such as metal-oxide-semiconductor (MOS) transistor devices. In one aspect, a transistor device comprises a channel region in a substrate partially delimited by a source and a drain junction at a main surface of the substrate. A first dielectric layer stack is arranged on the channel region, such that an orthogonal projection of the first dielectric layer stack on the main surface defining a first area is between and does not overlap the junctions and. A second dielectric layer stack is formed laterally adjacent to and in contact with the first dielectric layer stack, such that an orthogonal projection of the second dielectric layer stack overlaps the junction and defines a second area. A metal gate layer is formed on the first and second dielectric layer stacks, where an orthogonal projection of the metal gate layer on the main surface overlaps the first area and the second area. The first dielectric layer stack has a larger capacitance than the second dielectric layer stack

A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained.

The disclosed technology generally relates to semiconductor devices, and more particularly to transistors comprising germanium (Ge) in the channel, and to methods of manufacturing thereof. In one aspect, a field-effect transistor (FET) comprises an active region comprising germanium (Ge) and a gate stack formed on the active region. The gate stack comprises a Si-comprising passivation layer formed on the active region, an interfacial dielectric layer comprising SiO, (x>0) formed on the passivation layer, a dielectric capping layer comprising an interface dipole-forming material formed on the interfacial dielectric layer, a high-k dielectric layer formed on the dielectric capping layer and a gate electrode layer formed on the high-k dielectric layer.

A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction it spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

A semiconductor device includes a substrate including a planar portion and a mesa portion over the planar portion; an oxide layer over the mesa portion; a ferroelectric material strip covering a protruding plane of the oxide layer and exposing a side plane of the oxide layer; and a gate strip over the ferroelectric material strip and overlapping the oxide layer.

A method includes: providing a Group III nitride-based substrate having a first major surface and a doped Group III nitride region; forming a first passivation layer configured as a hydrogen diffusion barrier on the first major surface; forming a first opening in the first passivation layer and exposing at least a portion of the doped Group III nitride region from the first passivation layer; activating a first doped Group III nitride region whilst the first passivation layer is located on the first major surface and the doped Group III nitride region is at least partly exposed from the first passivation layer; forming a second passivation layer on the first passivation layer and on the doped Group III nitride region; forming a second opening in the first and second passivation layers and exposing a portion of the doped Group III nitride region; and forming a contact in the second opening.