A wide band gap semiconductor device is proposed. The wide band gap semiconductor device includes a wide band gap semiconductor body having a first surface and a second surface opposite to the first surface along a vertical direction. A gate electrode structure is arranged in an active transistor area. The gate electrode structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the wide band gap semiconductor body. A gate interconnection structure is arranged outside of the active transistor area. The gate interconnection structure includes an interconnection electrode and an interconnection dielectric arranged between the interconnection electrode and the wide band gap semiconductor body. Dielectric constants of a main dielectric component of at least two of i) a part of the gate interconnection dielectric, or ii) a first part of the gate dielectric, or iii) a second part of the gate dielectric differ from one another.

A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.

A method for producing a semiconductor device includes forming a first insulating film around a fin-shaped semiconductor layer and forming a pillar-shaped semiconductor layer and forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer. A metal-semiconductor compound is formed on the second diffusion layer. A first metal is deposited to form a gate electrode and a gate line. Second and third metal films are deposited to form a first contact in which the second metal film surrounds a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second contact connects an upper portion of the first contact and an upper portion of the pillar-shaped semiconductor layer. A third contact is formed on the gate line.

A semiconductor device includes a pillar-shaped semiconductor layer and a first gate insulating film around the pillar-shaped semiconductor layer. A metal gate electrode is around the first gate insulating film and a metal gate line is connected to the gate electrode. A second gate insulating film is around a sidewall of an upper portion of the pillar-shaped semiconductor layer and a first contact made of a second metal surrounds the second gate insulating film. An upper portion of the first contact is electrically connected to an upper portion of the pillar-shaped semiconductor layer, and a third contact resides on the metal gate line. A lower portion of the third contact is made of the second metal.

A semiconductor device includes: a semiconductor substrate including an active region and a gate structure on the active region. The gate structure includes a gate insulating film; a work function adjusting film on the first gate insulating film; a separation film on the work function adjusting film; and an oxygen capturing film on the separation film and configured to capture oxygen introduced from the outside of the first gate structure. The oxygen capturing film is spaced apart from a top surface of the first gate insulating film by about 70 to about 80 .

The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET).

A method for producing a semiconductor device includes forming a first insulating film around a fin-shaped semiconductor layer and forming a pillar-shaped semiconductor layer and forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer. A metal-semiconductor compound is formed on the second diffusion layer. A first metal is deposited to form a gate electrode and a gate line. Second and third metal films are deposited to form a first contact in which the second metal film surrounds a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second contact connects an upper portion of the first contact and an upper portion of the pillar-shaped semiconductor layer. A third contact is formed on the gate line.

In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.

Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.