One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

A double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a reverse voltage blocking diode inherent in the structure and without requiring metal connections for the ESD and reverse voltage blocking diode protections.

A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

A silicon-controlled rectifier (SCR) includes a first-type field, a second-type first field and a second-type second field disconnectedly formed in a first-type well; an entire first-type doped region formed within the first-type field; a segmented second-type doped region formed within the second-type first field; and a segmented first-type doped region formed within the second-type second field.

A combined semiconductor controlled circuit (CSCC) includes a semiconductor controlled switch (SCS). The SCS includes anode, cathode, anode gate and cathode gate terminals connected to P.sub.1 anode, N.sub.2 cathode, N.sub.1 anode gate and P.sub.2 cathode gate layers. The SCS also includes P-N junctions between P.sub.1 anode and N.sub.1 anode gate layers, N.sub.1 anode gate and P.sub.2 cathode gate layers and P.sub.2 cathode gate and N.sub.2 cathode layers. The CSCC also includes a Zener diode having a current path flowing from the cathode terminal to the anode gate terminal, a feedback resistor connecting cathode and cathode gate terminals and a substrate. A solid-state spark chamber includes a CSCC, a DC bias voltage source and an RC load having a parallel-connected load resistor and capacitor. The solid-state spark chamber also includes a plurality of measurement terminals and a ground. A method of making a solid-state spark chamber includes connecting the above components.

An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.

A semiconductor device includes a semiconductor layer of a first conductivity type that has a main surface and that includes a device region, a base region of a second conductivity type that is formed in a surface layer portion of the main surface at the device region, a source region of the first conductivity type that is formed in a surface layer portion of the base region at an interval inward from a peripheral portion of the base region and that defines a channel region with the semiconductor layer, a base contact region of the second conductivity type that is formed in a region different from the source region at the surface layer portion of the base region and that has an impurity concentration exceeding an impurity concentration of the base region, a well region of the first conductivity type that is formed in the surface layer portion of the main surface at an interval from the base region at the device region and that defines a drift region with the base region, a drain region of the first conductivity type that is formed in a surface layer portion of the well region, an impurity region of the second conductivity type that is formed in the surface layer portion of the well region and that is electrically connected to the drain region, and a gate structure that has a gate insulating film covering the channel region on the main surface and a gate electrode facing the channel region on the gate insulating film and electrically connected to the source region and the base contact region.

Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, and a plurality of n-type wells that each extend from the upper surface into the semiconductor body, wherein a total area of electrical insulator disposed between the p-type wells and the adjacent semiconductor body is greater than a total area of electrical insulator disposed between the n-type wells and the adjacent semiconductor body.

A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.